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公开(公告)号：US09825636B1
公开(公告)日：2017-11-21
申请号：US15299016
申请日：2016-10-20
申请人： ARM Limited
IPC分类号： H03L7/00
摘要： An apparatus for synchronizing an input signal that is asynchronous to a clock signal received by the apparatus. The apparatus comprising selection circuitry configured to select the input signal and to generate a pair of intermediate signals associated with the selected input signal. The apparatus also comprising resolution circuitry configured to provide differential signals based on the pair of intermediate signals and to resolve meta-stability associated with the differential signals. The apparatus also comprising arbiter circuitry configured to determine a dominant value associated with the differential signals and to generate an intermediate output signal based on the determination. The apparatus further comprising latching circuitry configured to generate an output signal based on the intermediate output signal.
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公开(公告)号：US09912338B1
公开(公告)日：2018-03-06
申请号：US15482456
申请日：2017-04-07
申请人： ARM Limited
CPC分类号： H03L7/00 , H03K3/0375 , H03K3/356113 , H03K5/135 , H03K2005/00286
摘要： A circuit to sample an input signal in an asynchronous clock domain. The apparatus includes a first latch configured to favor resolving to a logical high level and a second latch configured to favor resolving to a logical low level. The circuit includes a pullup pMOSFET, and first and second pMOSFETs. The first pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to a first input port of the first latch, and a drain terminal coupled to a second output port of the second latch. The second pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to the second output port of the second latch, and a drain terminal coupled to the first input port of the first latch.
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公开(公告)号：US20170117022A1
公开(公告)日：2017-04-27
申请号：US15401588
申请日：2017-01-09
申请人： ARM Limited
CPC分类号： G11C7/1012 , G11C5/141 , G11C8/06 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C29/702
摘要： Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.
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公开(公告)号：US20180074116A1
公开(公告)日：2018-03-15
申请号：US15817643
申请日：2017-11-20
申请人： ARM Limited
发明人： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC分类号： G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
摘要： Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
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公开(公告)号：US20170045576A1
公开(公告)日：2017-02-16
申请号：US14824093
申请日：2015-08-12
申请人： ARM Limited
发明人： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC分类号： G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
摘要： Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
摘要翻译： 本文所描述的各种实现涉及用于实现关键路径建筑师的系统和方法。 在一个实现中，关键路径架构师可以利用具有处理器和存储器的系统来实现，所述处理器和存储器包括存储在其上的指令，当由处理器执行时，处理器和存储器使处理器分析集成电路的定时数据。 定时数据可以包括沿着集成电路的路径的小区的转换时间。 指令可能导致处理器识别沿着集成电路的路径的单元的定时劣化的实例。 这些指令可能导致处理器推荐沿着具有定时劣化的路径的单元的实例的改变。
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公开(公告)号：US11586445B2
公开(公告)日：2023-02-21
申请号：US16698862
申请日：2019-11-27
申请人： Arm Limited
发明人： Shardendu Shekhar , Andy Wangkun Chen , Anil Kumar Baratam , James Dennis Dodrill , Yew Keong Chong
摘要： Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.
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公开(公告)号：US20210157603A1
公开(公告)日：2021-05-27
申请号：US16698862
申请日：2019-11-27
申请人： Arm Limited
发明人： Shardendu Shekhar , Andy Wangkun Chen , Anil Kumar Baratam , James Dennis Dodrill , Yew Keong Chong
摘要： Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.
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公开(公告)号：US10187063B1
公开(公告)日：2019-01-22
申请号：US15826647
申请日：2017-11-29
申请人： Arm Limited
IPC分类号： H03K3/356 , H03K19/173 , H03K3/012
摘要： Various implementations described herein are directed to a sequential logic device having multiple stages. The sequential logic device may include a first stage having first transistors that are arranged to receive a data input signal and a clock signal and provide a first signal and a second signal based on the data input signal and the clock signal. The sequential logic device may include a second stage having second transistors that are arranged to receive the first signal from the first stage and provide an inverted first signal to a gate of a first pass transistor. The first pass transistor may allow the second signal to pass from the first stage to a second pass transistor based on the inverted first signal, and the second pass transistor may allow the second signal to pass from the first pass transistor to ground based on the clock signal.
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公开(公告)号：US09823298B2
公开(公告)日：2017-11-21
申请号：US14824093
申请日：2015-08-12
申请人： ARM Limited
发明人： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC分类号： G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
摘要： Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
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公开(公告)号：US09690889B2
公开(公告)日：2017-06-27
申请号：US15239991
申请日：2016-08-18
申请人： ARM LIMITED
CPC分类号： G06F17/5031 , G06F17/5081 , G06F2217/84
摘要： A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.
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