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    Data compressor logic circuit
    3.
    发明授权
    Data compressor logic circuit 有权

    公开(公告)号：US10756753B2

    公开(公告)日：2020-08-25

    申请号：US16170723

    申请日：2018-10-25

    申请人： Arm Limited

    发明人： Shardendu Shekhar ,  Andy Wangkun Chen ,  Yew Keong Chong

    IPC分类号： G06F7/50 ,  H03K19/21 ,  H03M7/00 ,  H03K19/20 ,  H03M7/30 ,  H03K19/0944

    摘要： A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

    Data compressor logic circuit
    5.
    发明授权
    Data compressor logic circuit 有权

    公开(公告)号：US11831341B2

    公开(公告)日：2023-11-28

    申请号：US17001580

    申请日：2020-08-24

    申请人： Arm Limited

    发明人： Shardendu Shekhar ,  Andy Wangkun Chen ,  Yew Keong Chong

    IPC分类号： H03M7/00 ,  H03K19/0944 ,  H03K19/20 ,  H03K19/21 ,  H03M7/30

    CPC分类号： H03M7/005 ,  H03K19/0944 ,  H03K19/20 ,  H03K19/215 ,  H03M7/6011

    摘要： A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

    Data Compressor Logic Circuit
    6.
    发明申请
    Data Compressor Logic Circuit 审中-公开

    公开(公告)号：US20200136643A1

    公开(公告)日：2020-04-30

    申请号：US16170723

    申请日：2018-10-25

    申请人： Arm Limited

    发明人： Shardendu Shekhar ,  Andy Wangkun Chen ,  Yew Keong Chong

    IPC分类号： H03M7/00 ,  H03K19/20 ,  H03K19/21 ,  H03K19/0944 ,  H03M7/30

    摘要： A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

    Critical Path Architect
    8.
    发明申请
    Critical Path Architect 有权
    关键路径建筑师

    公开(公告)号：US20170045576A1

    公开(公告)日：2017-02-16

    申请号：US14824093

    申请日：2015-08-12

    申请人： ARM Limited

    发明人： Satheesh Balasubramanian ,  Shardendu Shekhar ,  James Dennis Dodrill ,  Sainarayanan Karatholuvu Suryanarayanan

    IPC分类号： G01R31/28 ,  G06F17/50

    CPC分类号： G01R31/2882 ,  G01R31/31725 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/82 ,  G06F2217/84

    摘要： Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.

    摘要翻译： 本文所描述的各种实现涉及用于实现关键路径建筑师的系统和方法。 在一个实现中，关键路径架构师可以利用具有处理器和存储器的系统来实现，所述处理器和存储器包括存储在其上的指令，当由处理器执行时，处理器和存储器使处理器分析集成电路的定时数据。 定时数据可以包括沿着集成电路的路径的小区的转换时间。 指令可能导致处理器识别沿着集成电路的路径的单元的定时劣化的实例。 这些指令可能导致处理器推荐沿着具有定时劣化的路径的单元的实例的改变。