公开(公告)号：US08083954B2

公开(公告)日：2011-12-27

申请号：US12131932

申请日：2008-06-03

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H01B13/00

CPC classification number: B32B37/226 ,  B32B38/06 ,  B32B2305/342 ,  B32B2457/08 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83132 ,  H05K1/023 ,  H05K1/185 ,  H05K1/188 ,  H05K3/025 ,  H05K2201/0355 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611

Abstract: A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer.

Abstract translation: 一种用于制造部件嵌入式PCB的方法包括：提供其上镀有电镀金属层的载体板; 将电子部件设置在载体板的电镀金属层上; 通过电介质膜将金属层层叠在其上设置有电子部件的电镀金属层和载体板上; 移除载体板并暴露电镀金属层; 并且将金属层和电镀金属层中的至少一个图案化为电路层。

公开(公告)号：US07875809B2

公开(公告)日：2011-01-25

申请号：US11766194

申请日：2007-06-21

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H05K1/00

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A circuit board includes a core layer substrate having a plated through hole filled with a dielectric material. The plated through hole has a sidewall coated with an inner electroless copper layer, and an electroplated metal layer plated on the inner electroless copper layer before the plated through hole is filled with the dielectric material. The outer portion of the filled plated through hole is thicker than the center portion and tapered toward the center portion to form a depressed surface on the filled plated through hole. The core layer substrate is covered with a patterned electroless copper layer and a patterned electroplated copper layer that connect with the inner electroless copper layer and electroplated metal layer of the plated through hole. The patterned electroplated copper layer forms a flat copper pad above the plated through hole.

Abstract translation: 电路板包括具有填充有介电材料的电镀通孔的芯层基板。 电镀通孔具有涂覆有内部化学镀铜层的侧壁和在电镀通孔填充有电介质材料之前镀在内部化学镀铜层上的电镀金属层。 填充电镀通孔的外部比中心部分厚，并且朝向中心部分逐渐变细，以在填充的电镀通孔上形成凹陷表面。 芯层衬底被覆有图案化的无电铜层和与电镀通孔的内部化学镀铜层和电镀金属层连接的图案化电镀铜层。 图案化的电镀铜层在电镀通孔上方形成平坦的铜焊盘。

公开(公告)号：US20100307666A1

公开(公告)日：2010-12-09

申请号：US12479811

申请日：2009-06-07

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC: B32B37/00

CPC classification number: B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

Abstract: A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

Abstract translation: 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

公开(公告)号：US20100075497A1

公开(公告)日：2010-03-25

申请号：US12236493

申请日：2008-09-23

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H01L21/44 ,  H01L21/288

CPC classification number: H05K3/242 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2203/1476 ,  H05K2203/1581

Abstract: A non-plating line (NPL) plating method is provided. The NPL plating method is featured in that at first it forms a circuit layer on a bump side only, and therefore a plating current can be transmitted via a plating metal layer on a ball side to the circuit layer (enclosed by an insulation layer, e.g., a solder resist or a photoresist) on the bump side, and thus forming a protection layer, e.g., plating gold, on the plating metal layer on the circuit layer and the ball side. In such a way, the plating gold is formed after the insulation layer, so that there won't be any plating gold existed beneath the insulation layer of the bump side (connected with dies). Hence, the insulation layer can be prevented from dropping off from the protection layer, i.e., the plating gold, and thus the reliability of the products can be improved.

Abstract translation: 提供非电镀线（NPL）电镀方法。 NPL镀覆方法的特征在于，它首先仅在凸块侧形成电路层，因此电镀电流可以通过球侧的电镀金属层传输到电路层（由绝缘层包围，例如 ，阻焊剂或光致抗蚀剂），从而在电路层和球侧的电镀金属层上形成保护层，例如镀金。 以这种方式，在绝缘层之后形成电镀金，使得在凸起侧（与模具连接）的绝缘层下方不存在镀金。 因此，可以防止绝缘层从保护层即电镀金脱落，从而可以提高产品的可靠性。

公开(公告)号：US20100170088A1

公开(公告)日：2010-07-08

申请号：US12725460

申请日：2010-03-17

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H05K3/10

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.

Abstract translation: 制造具有电镀通孔（PTH）芯层衬底和层叠多层盲孔的板的结构和方法。 可以实现比常规方法更多的盲孔堆叠层。 具有高密度芯层的板的制造方法包括以下：在制造PTH之后，填充在芯层的PTH内部的填充材料被部分地去除，直到PTH已经通过蚀刻达到适当的平坦凹陷; 然后进行图像转印和图案电镀，以在芯层基板正在形成电路层时填充并使凹陷部分达到所需厚度以形成铜焊盘（过镀层）; 最后使用无电镀铜和图案电镀制成产品。

公开(公告)号：US08161639B2

公开(公告)日：2012-04-24

申请号：US12895824

申请日：2010-09-30

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H01K3/10

CPC classification number: H05K3/4679 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/09918 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.

Abstract translation: 公开了一种用于制造嵌入式电路的层间导电结构的方法。 根据本发明的嵌入式电路的层间导电结构的制造方法，在层叠第一和第二层压板之前不形成激光共形掩模。 相反，在第一和第二层压板层压之后，直接进行激光钻孔工艺以形成通孔。 以这种方式，即使在第一和第二层压板之间存在偏移对准的情况下，也可以在不改善层间偏移值的情况下降低层压板的不同层之间短路的风险。

公开(公告)号：US20110083323A1

公开(公告)日：2011-04-14

申请号：US12895824

申请日：2010-09-30

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K3/00

CPC classification number: H05K3/4679 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/09918 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.

Abstract translation: 公开了一种用于制造嵌入式电路的层间导电结构的方法。 根据本发明的嵌入式电路的层间导电结构的制造方法，在层叠第一和第二层压板之前不形成激光共形掩模。 相反，在第一和第二层压板层压之后，直接进行激光钻孔工艺以形成通孔。 以这种方式，即使在第一和第二层压板之间存在偏移对准的情况下，也可以在不改善层间偏移值的情况下降低层压板的不同层之间短路的风险。

公开(公告)号：US20100309608A1

公开(公告)日：2010-12-09

申请号：US12479810

申请日：2009-06-07

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC: H01M6/14

CPC classification number: H01G4/01 ,  H01G4/005 ,  H01G4/06 ,  H01G4/228

Abstract: A buried capacitor structure including a first conductive metal layer, a first dielectric film, a capacitor, a second dielectric film, and a second conductive metal layer, which are stacked in sequence, wherein the capacitor is buried between the first dielectric film and the second dielectric film, the first conductive metal layer is formed into a first circuit pattern, the second conductive metal layer is formed into a second circuit pattern. The capacitor is a planar comb-shaped capacitor with a positive electrode, a negative electrode, and a capacitor paste filled between the positive electrode and the negative electrode, wherein the positive electrode includes a positive electrode end and a plurality of positive comb branches, the negative electrode includes a negative electrode end and a plurality of negative comb branches, and the positive branches and the negative branches are parallel to and separated from each other.

Abstract translation: 一种埋置电容器结构，其包括依次层叠的第一导电金属层，第一电介质膜，电容器，第二电介质膜和第二导电金属层，其中，所述电容器埋设在所述第一电介质膜和所述第二电介质膜之间 电介质膜，第一导电金属层形成为第一电路图案，第二导电金属层形成第二电路图案。 电容器是具有正极，负极和填充在正极和负极之间的电容器浆料的平面梳状电容器，其中正极包括正极端和多个正梳分支， 负极包括负极端和多个负梳分支，并且正分支和负分支彼此平行并分离。

公开(公告)号：US20100283145A1

公开(公告)日：2010-11-11

申请号：US12435409

申请日：2009-05-05

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu ,  Wen-Chun Huang

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu ,  Wen-Chun Huang

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stack structure with copper bumps on an integrated circuit board is disclosed. The stack structure includes a plurality of insulating layers and a plurality of conductive layers which are stacked alternately. The uppermost conductive layer has copper bumps as copper pillar pins for soldering the chip pins of an integrated circuit chip. Because the copper bumps have a certain height, the distance between the copper bumps and the chip pins is shortened, and therefore the solders needed for soldering may be reduced. Also, the shape of the solders is a long strap instead of spheroid due to the cohesion force between the copper bump surfaces and the solders so that the distance between the solders is scaled down and the gaps between the pins are reduced. Thus, the entire size of the integrated circuit board may also be miniatured.

Abstract translation: 公开了一种在集成电路板上具有铜凸块的堆叠结构。 堆叠结构包括交替堆叠的多个绝缘层和多个导电层。 最上层的导电层具有作为用于焊接集成电路芯片的芯片引脚的铜柱引脚的铜凸块。 由于铜凸块具有一定的高度，所以铜凸块和芯片销之间的距离缩短，因此焊接所需的焊料可能会降低。 此外，由于铜凸块表面和焊料之间的内聚力，焊料的形状是长带而不是球体，使得焊料之间的距离被缩小，并且销之间的间隙减小。 因此，集成电路板的整体尺寸也可以是微型的。

公开(公告)号：US07871892B2

公开(公告)日：2011-01-18

申请号：US12479811

申请日：2009-06-07

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC: H01L21/20

CPC classification number: B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

Abstract: A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

Abstract translation: 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。