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公开(公告)号：US08197659B2
公开(公告)日：2012-06-12
申请号：US13240626
申请日：2011-09-22
Applicant: Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
Inventor： Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
CPC classification number: C25D5/02 , H05K3/108 , H05K3/421 , H05K3/423 , H05K3/429 , H05K3/4661 , H05K2201/0116 , H05K2201/09563 , H05K2203/025 , H05K2203/0257 , Y10T29/49124 , Y10T428/24917 , Y10T428/24926 , Y10T428/249955 , Y10T428/249958
Abstract: A method for manufacturing a multilayer printed circuit board including providing a core substrate having a penetrating-hole, forming an electroless plated film on a surface of the substrate and an inner wall surface of the penetrating-hole, electrolytically plating the substrate while moving with respect to the surface of the substrate an insulating member in contact with the surface of the substrate such that an electrolytic plated film is formed on the electroless plated film, an opening space inside the penetrating-hole is filled with an electrolytic material, and a through-hole conductor structure is formed in the penetrating-hole, forming an etching resist having an opening pattern on the electrolytic plated film, and removing an exposed pattern of the electrolytic plated film exposed by the opening pattern and a pattern of the electroless plated film under the exposed pattern such that a conductor circuit is formed on the surface of the substrate.
Abstract translation: 一种多层印刷电路板的制造方法，其特征在于，具有提供具有贯通孔的芯基板，在所述基板的表面上形成无电镀膜和所述贯通孔的内壁面，对所述基板进行电解电镀，同时相对于 在所述基板的表面上与所述基板的表面接触的绝缘构件，使得在所述无电镀膜上形成电解电镀膜，所述贯通孔内的开口空间填充有电解材料， 在导电孔中形成空穴导体结构，在电解镀膜上形成具有开口图案的抗蚀剂，并且除去由开口图案露出的电解电镀膜的露出图案，以及将化学镀膜的图案 使得在基板的表面上形成导体电路。
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公开(公告)号：US20090107847A1
公开(公告)日：2009-04-30
申请号：US12342866
申请日：2008-12-23
Applicant: Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
Inventor： Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
IPC: C25D5/00
CPC classification number: C25D5/02 , H05K3/108 , H05K3/421 , H05K3/423 , H05K3/429 , H05K3/4661 , H05K2201/0116 , H05K2201/09563 , H05K2203/025 , H05K2203/0257 , Y10T29/49124 , Y10T428/24917 , Y10T428/24926 , Y10T428/249955 , Y10T428/249958
Abstract: A plating method includes providing an article in a plating bath, covering a surface of the article with an insulating member in the plating bath, and electrolytically plating the article while moving one of the insulating member and the article relative to each other.
Abstract translation: 电镀方法包括在镀浴中提供物品，在电镀槽中用绝缘构件覆盖制品的表面，以及在使绝缘构件和制品相对于彼此移动中的同时对制品进行电解电镀。
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公开(公告)号：US20090107711A1
公开(公告)日：2009-04-30
申请号：US12342772
申请日：2008-12-23
Applicant: Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
Inventor： Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
CPC classification number: C25D5/02 , H05K3/108 , H05K3/421 , H05K3/423 , H05K3/429 , H05K3/4661 , H05K2201/0116 , H05K2201/09563 , H05K2203/025 , H05K2203/0257 , Y10T29/49124 , Y10T428/24917 , Y10T428/24926 , Y10T428/249955 , Y10T428/249958
Abstract: A multilayer printed circuit board has an insulation layer, a first conductor layer provided over a first side of the insulation layer, a second conductor layer provided over a second side of the insulation layer opposite to the first side, and multiple filled vias electrically connecting the first conductor layer and the second conductor layer. The filled vias have upper surfaces, respectively, and each of the upper surfaces is made such that a difference between a lowest point and a highest point of each of the upper surfaces is less than or equal to about 7 μm.
Abstract translation: 多层印刷电路板具有绝缘层，设置在绝缘层的第一侧上的第一导体层，设置在与第一侧相反的绝缘层的第二侧上的第二导体层，以及多个填充的通孔， 第一导体层和第二导体层。 填充的通孔分别具有上表面，并且每个上表面被制成使得每个上表面的最低点和最高点之间的差小于或等于约7μm。
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公开(公告)号：US07481909B2
公开(公告)日：2009-01-27
申请号：US11232906
申请日：2005-09-23
Applicant: Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
Inventor： Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
CPC classification number: C25D5/02 , H05K3/108 , H05K3/421 , H05K3/423 , H05K3/429 , H05K3/4661 , H05K2201/0116 , H05K2201/09563 , H05K2203/025 , H05K2203/0257 , Y10T29/49124 , Y10T428/24917 , Y10T428/24926 , Y10T428/249955 , Y10T428/249958
Abstract: A plating apparatus includes a plating bath, a member provided in the plating bath and a moving device. The member is configured to cover a surface to be plated. A moving device is configured to relatively move the member or the surface to change an area of the surface covered by the member.
Abstract translation: 电镀装置包括镀浴，设置在电镀槽中的部件和移动装置。 该构件构造成覆盖待镀表面。 移动装置构造成使构件或表面相对移动以改变由构件覆盖的表面的区域。
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公开(公告)号：US20060065534A1
公开(公告)日：2006-03-30
申请号：US11232906
申请日：2005-09-23
Applicant: Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
Inventor： Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
CPC classification number: C25D5/02 , H05K3/108 , H05K3/421 , H05K3/423 , H05K3/429 , H05K3/4661 , H05K2201/0116 , H05K2201/09563 , H05K2203/025 , H05K2203/0257 , Y10T29/49124 , Y10T428/24917 , Y10T428/24926 , Y10T428/249955 , Y10T428/249958
Abstract: A plating apparatus includes a plating bath, a member provided in the plating bath and a moving device. The member is configured to cover a surface to be plated. A moving device is configured to relatively move the member or the surface to change an area of the surface covered by the member.
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Patent Agency Ranking
公开(公告)号：US08536696B2
公开(公告)日：2013-09-17
申请号：US12546950
申请日：2009-08-25
Applicant: Naohiro Hirose , Hitoshi Ito , Yoshiyuki Iwata , Masanori Kawade , Hajime Yazu
Inventor： Naohiro Hirose , Hitoshi Ito , Yoshiyuki Iwata , Masanori Kawade , Hajime Yazu
CPC classification number: H01L23/49811 , H01L2224/05001 , H01L2224/05572 , H01L2224/1134 , H01L2224/13099 , H01L2924/00013 , H01L2924/01019 , H01L2924/01322 , H01L2924/15312 , H05K1/111 , H05K1/112 , H05K3/28 , H05K3/321 , H05K3/3421 , H05K3/384 , H05K3/4602 , H05K2201/09381 , H05K2201/09472 , H05K2201/09509 , H05K2201/096 , H05K2201/0979 , H05K2201/10318 , Y10T428/239
Abstract: A package substrate including an outermost interlayer resin insulating layer, a pad structure formed on the outermost interlayer resin insulating layer, a conductive connecting pin for establishing an electrical connection with another substrate, the conductive connecting pin being secured to the pad structure via a solder, and via holes formed through the outermost interlayer resin insulating layer and for electrically connecting the pad structure to one or more conductive circuits formed below the outermost interlayer resin insulating layer, the via holes being positioned directly below the pad structure.
Abstract translation: 包括最外层间树脂绝缘层，形成在最外层间树脂绝缘层上的焊盘结构的封装基板，用于与另一基板建立电连接的导电连接引脚，所述导电连接引脚通过焊料固定在焊盘结构上， 以及通过最外层间树脂绝缘层形成的通孔，并且将焊盘结构电连接到在最外层间树脂绝缘层下形成的一个或多个导电电路，通孔位于焊盘结构的正下方。
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公开(公告)号：US07897027B2
公开(公告)日：2011-03-01
申请号：US12342866
申请日：2008-12-23
Applicant: Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
Inventor： Toru Nakai , Satoru Kawai , Hiroshi Niwa , Yoshiyuki Iwata
CPC classification number: C25D5/02 , H05K3/108 , H05K3/421 , H05K3/423 , H05K3/429 , H05K3/4661 , H05K2201/0116 , H05K2201/09563 , H05K2203/025 , H05K2203/0257 , Y10T29/49124 , Y10T428/24917 , Y10T428/24926 , Y10T428/249955 , Y10T428/249958
Abstract: A plating method includes providing an article in a plating bath, covering a surface of the article with an insulating member in the plating bath, and electrolytically plating the article while moving one of the insulating member and the article relative to each other.
Abstract translation: 电镀方法包括在镀浴中提供物品，在电镀槽中用绝缘构件覆盖制品的表面，以及在使绝缘构件和制品相对于彼此移动中的同时对制品进行电解电镀。
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公开(公告)号：US07868564B2
公开(公告)日：2011-01-11
申请号：US12065145
申请日：2005-10-31
Applicant: Yoshiyuki Iwata , Satoru Yamada
Inventor： Yoshiyuki Iwata , Satoru Yamada
IPC: H05H9/00
Abstract: A linearity of a voltage change to a tuner insertion amount is verified for at least one of a plurality of tuners. Based on the voltage change linearity, individual voltage change data corresponding to respective insertion amounts are calculated for each of the plurality of tuners through a proportional calculation. A combination of auto-tuners and a combination of respective insertion amounts of the auto-tuners are determined using the individual voltage change data, and an adequacy of the determined combinations is verified through a direct three-dimensional electromagnetic field calculation. The combinations are determined on a condition that, when the individual voltage change data of nominated tuners are added together, respective voltage changes attributed to the nominated tuners are cancelled out to allow an entire voltage distribution to have substantially no change.
Abstract translation: 对于多个调谐器中的至少一个，验证对调谐器插入量的电压变化的线性度。 基于电压变化线性度，通过比例计算对于多个调谐器中的每一个计算对应于各个插入量的各个电压变化数据。 使用单独的电压变化数据来确定自动调谐器和自动调谐器的相应插入量的组合的组合，并且通过直接三维电磁场计算来验证所确定的组合的充分性。 这些组合是在将指定的调谐器的各个电压变化数据相加在一起的情况下确定的，抵消归因于指定的调谐器的各自的电压变化，以允许整个电压分布基本上没有变化。
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公开(公告)号：US07847393B2
公开(公告)日：2010-12-07
申请号：US12257501
申请日：2008-10-24
Applicant: Naohiro Hirose , Hitoshi Ito , Yoshiyuki Iwata , Masanori Kawade , Hajime Yazu
Inventor： Naohiro Hirose , Hitoshi Ito , Yoshiyuki Iwata , Masanori Kawade , Hajime Yazu
IPC: H01L23/48 , H01L21/4763
CPC classification number: H01L23/49811 , H01L2224/05001 , H01L2224/05572 , H01L2224/1134 , H01L2224/13099 , H01L2924/00013 , H01L2924/01019 , H01L2924/01322 , H01L2924/15312 , H05K1/111 , H05K1/112 , H05K3/28 , H05K3/321 , H05K3/3421 , H05K3/384 , H05K3/4602 , H05K2201/09381 , H05K2201/09472 , H05K2201/09509 , H05K2201/096 , H05K2201/0979 , H05K2201/10318 , Y10T428/239
Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.
Abstract translation: 一种包含衬底的封装衬底310，该衬底设置有导体层5，导电连接销100被布置成与母板建立电连接并固定到衬底的表面，其中提供用于固定导电连接销的衬垫16 用于封装衬底310.衬垫16被具有开口18的有机树脂绝缘层15覆盖，衬垫16通过该开口部分地暴露于外部。 导电连接销100通过导电粘合剂17通过开口固定到暴露于外部的焊盘，从而防止例如当执行安装时发生例如导电连接销100从基板的溶液。
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公开(公告)号：US07736457B2
公开(公告)日：2010-06-15
申请号：US11567344
申请日：2006-12-06
Applicant: Yoshiyuki Iwata
Inventor： Yoshiyuki Iwata
CPC classification number: B32B38/10 , B32B2310/0843 , B32B2457/08 , H05K1/115 , H05K3/20 , H05K3/4602 , H05K3/4682 , H05K2201/09527 , H05K2201/09563 , H05K2201/096 , H05K2203/0554 , H05K2203/1536 , Y10T29/49165 , Y10T156/1056 , Y10T156/1057
Abstract: The present invention intends to provide a novel printed wiring board manufacturing method by which printed wiring boards can be manufactured with efficiency. A method of manufacturing a printed wiring board (FIG. 1B) according to the present invention includes a step for preparing two sets of copper clad laminates (FIG. 2A), a step for bonding the copper clad laminates (FIG. 2B), steps for forming lands on both surfaces of a bonded laminate (FIGS. 2C to 2E), steps for forming respective resin layers on both surfaces of the bonded laminate and forming via hole openings to form respective via holes (FIGS. 2F to 2L), a step for forming a resin layer and forming a via hole opening to form a via hole (FIG. 2M), a step for separating the bonded laminate from each other (FIG. 2N) and steps for forming via hole openings from the bonded surface of the separated laminate to form via holes (FIGS. 2O to 2T). Via holes (33-1, 33-2) formed on the resin layer and a via hole (42) formed on the laminate are opened in the opposite directions.
Abstract translation: 本发明旨在提供一种能够有效地制造印刷电路板的新颖的印刷线路板制造方法。 根据本发明的制造印刷电路板（图1B）的方法包括制备两组铜包覆层压板的步骤（图2A），用于粘合覆铜层压板的步骤（图2B），步骤 用于在接合层压体的两个表面上形成焊盘（图2C至2E），用于在接合层叠体的两个表面上形成各个树脂层并形成通孔开口以形成相应的通孔的步骤（图2F至2L）， 用于形成树脂层并形成通孔开口以形成通孔的步骤（图2M），用于将接合的层压体彼此分离的步骤（图2N）和从接合表面形成通孔开口的步骤 分离的层压体以形成通孔（图20至图2T）。 形成在树脂层上的通孔（33-1,33-2）和形成在层叠体上的通孔（42）沿相反方向打开。
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