公开(公告)号：US07294043B2

公开(公告)日：2007-11-13

申请号：US11470407

申请日：2006-09-06

申请人： Chen-Shien Chen ,  Yai-Yei Huang ,  Ming-Hsiang Kao ,  Yih-Shung Lin ,  Winata Karta Tjandra

发明人： Chen-Shien Chen ,  Yai-Yei Huang ,  Ming-Hsiang Kao ,  Yih-Shung Lin ,  Winata Karta Tjandra

IPC分类号： B24B49/00

CPC分类号： B24B21/04 ,  B24B37/345 ,  B24B49/02

摘要： A CMP apparatus and process sequence. The CMP apparatus includes multiple polishing pads or belts and an in-line metrology tool which is interposed between adjacent polishing pads or belts in the apparatus. A material layer on each of multiple wafers is successively polished on the polishing pads or belts. The metrology tool is used to measure the thickness of a material layer being polished on each of successive wafers in a lot prior to the final polishing step, in order to precisely polish the layer to a desired target thickness at the final polishing step. This renders unnecessary an additional process cycle to polish the layer on each wafer to the desired target thickness. The metrology tool may be modularized as a unit with the polishing pads or belts.

摘要翻译： CMP装置和处理顺序。 CMP装置包括多个抛光垫或带以及插入在装置中的相邻抛光垫或带之间的在线计量工具。 在多个晶片的每一个上的材料层在抛光垫或带上连续抛光。 测量工具用于测量在最终抛光步骤之前在批次中的每个连续晶片上抛光的材料层的厚度，以便在最终抛光步骤中将层精确抛光到所需目标厚度。 这使得不需要额外的处理循环来将每个晶片上的层抛光到期望的目标厚度。 测量工具可以模块化为具有抛光垫或带的单元。

公开(公告)号：US07004814B2

公开(公告)日：2006-02-28

申请号：US10804934

申请日：2004-03-19

申请人： Chen-Shien Chen ,  Yai-Yei Huang ,  Yean-Zhaw Chen ,  Kai-Hsiung Chen ,  Yih-Shung Lin

发明人： Chen-Shien Chen ,  Yai-Yei Huang ,  Yean-Zhaw Chen ,  Kai-Hsiung Chen ,  Yih-Shung Lin

IPC分类号： B24B1/00

CPC分类号： B24B37/042 ,  B24B49/00

摘要： A one-time feedback CMP process control method which contributes to uniformity in the quantity of material removed from wafers in a lot during semiconductor processing and is suitable for complex processes such as STI (shallow trench isolation) fabrication procedures, is disclosed. The method includes providing a plurality of wafers having a set of pilot wafers and a set of remaining wafers, polishing each of the pilot wafers according to an original process time, determining a compensation time for the pilot wafers, determining an update time by adding the compensation time to the original process time and polishing the set of remaining wafers according to the update time.

摘要翻译： 公开了一种有助于在半导体处理期间从批次中的晶片去除的材料的量的均匀性的一次性反馈CMP工艺控制方法，并且适用于诸如STI（浅沟槽隔离）制造程序的复杂工艺。 该方法包括提供具有一组导频晶片和一组剩余晶片的多个晶片，根据原始处理时间抛光每个导频晶片，确定导频晶片的补偿时间，通过将 补偿时间到原始处理时间，并根据更新时间抛光剩余的晶圆组。

公开(公告)号：US06943077B2

公开(公告)日：2005-09-13

申请号：US10408689

申请日：2003-04-07

申请人： Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Yih-Shung Lin ,  Cheng-Chung Lin ,  Chia-Hui Lin

发明人： Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Yih-Shung Lin ,  Cheng-Chung Lin ,  Chia-Hui Lin

IPC分类号： H01L21/02 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823468 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/823456 ,  H01L29/6656

摘要： A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

摘要翻译： 一种在半导体衬底上形成具有不同宽度的间隔物的方法，包括以下步骤：在衬底上设置第一间隔层，将第一间隔层限定为多个第一宽度的间隔物，并且在第 为第二间隔层预选的多个间隔物的第一间隔层，具有第二间隔层的预定数量的间隔物各自具有与第一宽度不同的第二宽度。

公开(公告)号：US06433435B1

公开(公告)日：2002-08-13

申请号：US09086884

申请日：1998-05-29

申请人： Yih-Shung Lin ,  Fu-Tai Liou

发明人： Yih-Shung Lin ,  Fu-Tai Liou

IPC分类号： H01L2348

摘要： A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

公开(公告)号：US06291344B1

公开(公告)日：2001-09-18

申请号：US09660738

申请日：2000-09-13

申请人： De-Dul Liao ,  Yih-Shung Lin

发明人： De-Dul Liao ,  Yih-Shung Lin

IPC分类号： H01L2144

CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/924 ,  H01L2924/00

摘要： Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the, atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA. Alternative embodiments are also disclosed in which the silicide is formed first, prior to the formation of additional titanium oxynitride by air exposure and RTA, or by sputter deposition. Each of these processes produces a high-quality barrier contact structure overlying a silicide film, where the barrier structure includes titanium oxynitride and titanium nitride.

摘要翻译： 在集成电路中形成具有阻挡层的铝 - 硅接触的方法被公开。 通过在接触底部的暴露的硅处形成的硅化物膜附近提供氧氮化钛层来增强阻挡层。 氮氧化钛可以通过在与接触中的硅接触的钛金属层上沉积低密度氮化钛膜而形成; 随后的空气暴露使得相对较大量的氧和氮进入氮化钛。 快速热退火（RTA）都在接触位置处引起硅化，并且还导致氧和氮被吸收到先前的钛/氮化钛界面，其中氧和氮与钛金属和氮气中的氮反应， 气氛形成氮氧化钛。 低密度钛氮化物也在RTA期间致密化。 还公开了另外的实施方案，其中在通过空气暴露和RTA形成额外的氮氧化钛之前，或通过溅射沉积，首先形成硅化物。 这些过程中的每一个产生覆盖硅化物膜的高质量的阻挡接触结构，其中阻挡结构包括氧氮化钛和氮化钛。

公开(公告)号：US5652464A

公开(公告)日：1997-07-29

申请号：US569392

申请日：1995-12-08

申请人： De-Dui Liao ,  Yih-Shung Lin

发明人： De-Dui Liao ,  Yih-Shung Lin

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/924

摘要： Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA. Alternative embodiments are also disclosed in which the silicide is formed first, prior to the formation of additional titanium oxynitride by air exposure and RTA, or by sputter deposition. Each of these processes produces a high-quality barrier contact structure overlying a silicide film, where the barrier structure includes titanium oxynitride and titanium nitride.

摘要翻译： 在集成电路中形成具有阻挡层的铝 - 硅接触的方法被公开。 通过在接触底部的暴露的硅处形成的硅化物膜附近提供氧氮化钛层来增强阻挡层。 氮氧化钛可以通过在与接触中的硅接触的钛金属层上沉积低密度氮化钛膜而形成; 随后的空气暴露使得相对较大量的氧和氮进入氮化钛。 快速热退火（RTA）都在接触位置处引起硅化，并且还导致氧和氮被吸收到先前的钛/氮化钛界面，其中氧和氮与大气中的钛金属和氮反应 以形成氮氧化钛。 低密度钛氮化物也在RTA期间致密化。 还公开了另外的实施方案，其中在通过空气暴露和RTA形成额外的氮氧化钛之前，或通过溅射沉积，首先形成硅化物。 这些过程中的每一个产生覆盖硅化物膜的高质量的阻挡接触结构，其中阻挡结构包括氧氮化钛和氮化钛。

公开(公告)号：US20060113616A1

公开(公告)日：2006-06-01

申请号：US11206613

申请日：2005-08-18

申请人： Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Yih-Shung Lin ,  Cheng-Chung Lin ,  Chia-Hui Lin

发明人： Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Yih-Shung Lin ,  Cheng-Chung Lin ,  Chia-Hui Lin

IPC分类号： H01L29/94

CPC分类号： H01L21/823468 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/823456 ,  H01L29/6656

摘要： A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

摘要翻译： 一种在半导体衬底上形成具有不同宽度的间隔物的方法，包括以下步骤：在衬底上设置第一间隔层，将第一间隔层限定为多个第一宽度的间隔物，并且在第 为第二间隔层预选的多个间隔物的第一间隔层，具有第二间隔层的预定数量的间隔物各自具有与第一宽度不同的第二宽度。

公开(公告)号：US07011929B2

公开(公告)日：2006-03-14

申请号：US10340245

申请日：2003-01-09

申请人： Ming-Ta Lei ,  Yih-Shung Lin ,  Ai-Sen Liu ,  Cheng-Chung Lin ,  Baw-Ching Perng ,  Chia-Hui Lin

发明人： Ming-Ta Lei ,  Yih-Shung Lin ,  Ai-Sen Liu ,  Cheng-Chung Lin ,  Baw-Ching Perng ,  Chia-Hui Lin

IPC分类号： H01L21/302

CPC分类号： H01L21/823468

摘要： A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

摘要翻译： 一种形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供形成在衬底上的多个栅极结构和基本上共形地覆盖栅极结构的多个电介质层; 暴露多个的第一选定部分，然后通过各向异性蚀刻穿过包括至少最上面的介电层的厚度部分以形成第一侧壁间隔物宽度; 暴露多个的第一后续选定部分，然后蚀刻通过至少最上层介电层的厚度部分; 并且暴露多个随后的第二部分，然后通过各向异性蚀刻穿过至少最上面的介电层的厚度部分以形成随后的侧壁间隔物宽度。

公开(公告)号：US20050208876A1

公开(公告)日：2005-09-22

申请号：US10804934

申请日：2004-03-19

申请人： Chen-Shien Chen ,  Yai-Yei Huang ,  Yean-Zhaw Chen ,  Kai-Hsiung Chen ,  Yih-Shung Lin

发明人： Chen-Shien Chen ,  Yai-Yei Huang ,  Yean-Zhaw Chen ,  Kai-Hsiung Chen ,  Yih-Shung Lin

IPC分类号： B24B37/04 ,  B24B49/00 ,  B24B51/00 ,  G05B19/04 ,  H01L21/304

CPC分类号： B24B37/042 ,  B24B49/00

摘要： A one-time feedback CMP process control method which contributes to uniformity in the quantity of material removed from wafers in a lot during semiconductor processing and is suitable for complex processes such as STI (shallow trench isolation) fabrication procedures, is disclosed. The method includes providing a plurality of wafers having a set of pilot wafers and a set of remaining wafers, polishing each of the pilot wafers according to an original process time, determining a compensation time for the pilot wafers, determining an update time by adding the compensation time to the original process time and polishing the set of remaining wafers according to the update time.

摘要翻译： 公开了一种有助于在半导体处理期间从批次中的晶片去除的材料的量的均匀性的一次性反馈CMP工艺控制方法，并且适用于诸如STI（浅沟槽隔离）制造程序的复杂工艺。 该方法包括提供具有一组导频晶片和一组剩余晶片的多个晶片，根据原始处理时间抛光每个导频晶片，确定导频晶片的补偿时间，通过将 补偿时间到原始处理时间，并根据更新时间抛光剩余的晶圆组。

公开(公告)号：US06207554B1

公开(公告)日：2001-03-27

申请号：US09351237

申请日：1999-07-12

申请人： Yi Xu ,  Jia Zhen Zheng ,  Jane C. M. Hui ,  Charles Lin ,  Yih Shung Lin

发明人： Yi Xu ,  Jia Zhen Zheng ,  Jane C. M. Hui ,  Charles Lin ,  Yih Shung Lin

IPC分类号： H01L214763

CPC分类号： H01L21/02164 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3185 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837

摘要： It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of fabricating multilevel metal structures using low dielectric constant materials. The present invention relates to an improved processing methods for stable and planar intermetal dielectrics, with low dielectric constants. The first embodiment uses a stabilizing adhesion layer between the bottom, low dielectric constant layer and the top dielectric layer. The advantages are: (i) improved adhesion and stability of the low dielectric layer and the top dielectric oxide (ii) over all layer thickness of the dielectric layers can be reduced, hence lowering the parasitic capacitance of these layers. In the second embodiment, the method uses a multi-layered “hard mask” on metal interconnect lines with a silicon oxynitride DARC, dielectric anti-reflective coating on top of metal. A double coating scheme of low dielectric constant insulators are used in this application. The third embodiment uses a hard mask stack over the interconnect metal lines, with a silicon oxynitride DARC costing on top of metal, and an adhesion layer between the low dielectric material and the top dielectric layer.

摘要翻译： 本发明的总体目的是提供一种制造半导体集成电路器件的改进方法，特别是通过描述使用低介电常数材料制造多层金属结构的改进方法。 本发明涉及一种具有低介电常数的稳定和平坦的金属间电介质的改进的处理方法。 第一实施例使用底部，低介电常数层和顶部介电层之间的稳定粘合层。 优点是：（i）可以降低介电层的所有层厚度上的低介电层和顶部电介质氧化物（ii）的粘附性和稳定性，因此降低这些层的寄生电容。 在第二实施例中，该方法在具有氮氧化硅DARC的金属互连线上使用多层“硬掩模”，金属顶部具有介电抗反射涂层。 本申请中使用低介电常数绝缘体的双重涂层方案。 第三实施例在互连金属线上使用硬掩模叠层，在金属顶部成本计算氮氧化硅DARC，以及低电介质材料和顶部电介质层之间的粘合层。