公开(公告)号：US09376713B2

公开(公告)日：2016-06-28

申请号：US12888917

申请日：2010-09-23

Applicant: Rashid Bashir ,  Yi-Shao Liu ,  Eric Salm ,  Woo-Jin Chang ,  Nicholas N. Watkins

Inventor： Rashid Bashir ,  Yi-Shao Liu ,  Eric Salm ,  Woo-Jin Chang ,  Nicholas N. Watkins

IPC: C12Q1/68 ,  B01L3/00 ,  B01L7/00 ,  B03C5/02 ,  B01L3/02

CPC classification number: C12Q1/6825 ,  B01L3/0241 ,  B01L3/5027 ,  B01L3/502746 ,  B01L3/502761 ,  B01L3/502784 ,  B01L7/52 ,  B01L2200/0668 ,  B01L2200/10 ,  B01L2200/143 ,  B01L2200/147 ,  B01L2300/0645 ,  B01L2300/0681 ,  B01L2300/0867 ,  B01L2300/1822 ,  B01L2300/1827 ,  B01L2400/0418 ,  B01L2400/0424 ,  B01L2400/084 ,  B03C5/026

Abstract: Provided are methods and devices for label-free detection of nucleic acids that are amplified by polymerase chain reaction. A solution containing the components necessary for a PCR is introduced to a microfluidic amplification chamber and an electric field applied to a confined region in which PCR occurs. PCR product generated in the confined region is detected by measuring an electrical parameter that is, for example, solution impedance. The devices and methods provided herein are used, for example, in assays to detect one or more pathogens or for point-of-care tests. In an aspect, the PCR product is confined to droplets and the assay relates to detecting an electrical parameter of a flowing droplet, thereby detecting PCR product without a label. In an aspect, the PCR occurs in the droplet.

Abstract translation: 提供了通过聚合酶链反应扩增的用于无标记检测核酸的方法和装置。 将含有PCR所需组分的溶液引入微流体扩增室，并施加到发生PCR的限制区域的电场。 通过测量例如溶液阻抗的电参数来检测在限制区域中产生的PCR产物。 本文提供的装置和方法例如用于检测一种或多种病原体或用于点护理测试的测定中。 在一方面，PCR产物被限制在液滴中，并且该测定涉及检测流动液滴的电参数，从而检测没有标签的PCR产物。 在一方面，PCR在液滴中发生。

公开(公告)号：US08723222B2

公开(公告)日：2014-05-13

申请号：US13548522

申请日：2012-07-13

Applicant: Sung Bum Bae ,  Eun Soo Nam ,  Jae Kyoung Mun ,  Sung Bock Kim ,  Hae Cheon Kim ,  Chull Won Ju ,  Sang Choon Ko ,  Jong-Won Lim ,  Ho Kyun Ahn ,  Woo Jin Chang ,  Young Rak Park

Inventor： Sung Bum Bae ,  Eun Soo Nam ,  Jae Kyoung Mun ,  Sung Bock Kim ,  Hae Cheon Kim ,  Chull Won Ju ,  Sang Choon Ko ,  Jong-Won Lim ,  Ho Kyun Ahn ,  Woo Jin Chang ,  Young Rak Park

IPC: H01L31/102

CPC classification number: H01L29/66446 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0883

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。

公开(公告)号：US20130020649A1

公开(公告)日：2013-01-24

申请号：US13548522

申请日：2012-07-13

Applicant: Sung Bum BAE ,  Eun Soo NAM ,  Jae Kyoung MUN ,  Sung Bock KIM ,  Hae Cheon KIM ,  Chull Won JU ,  Sang Choon KO ,  Jong-Won LIM ,  Ho Kyun AHN ,  Woo Jin CHANG ,  Young Rak PARK

Inventor： Sung Bum BAE ,  Eun Soo NAM ,  Jae Kyoung MUN ,  Sung Bock KIM ,  Hae Cheon KIM ,  Chull Won JU ,  Sang Choon KO ,  Jong-Won LIM ,  Ho Kyun AHN ,  Woo Jin CHANG ,  Young Rak PARK

IPC: H01L27/088 ,  H01L21/20 ,  H01L27/08

CPC classification number: H01L29/66446 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0883

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。

公开(公告)号：US07387955B2

公开(公告)日：2008-06-17

申请号：US11454721

申请日：2006-06-16

Applicant: Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

Inventor： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

IPC: H01L21/44

CPC classification number: H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

Abstract: A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract translation: 提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

公开(公告)号：US07183149B2

公开(公告)日：2007-02-27

申请号：US11180726

申请日：2005-07-14

Applicant: Ho Kyun Ahn ,  Jong Won Lim ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim

Inventor： Ho Kyun Ahn ,  Jong Won Lim ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim

IPC: H01L21/338

CPC classification number: H01L29/66856 ,  H01L29/66462

Abstract: Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.

Abstract translation: 提供了制造场效应晶体管（FET）的方法。 该方法包括以下步骤：在源极和漏极区域的衬底上形成欧姆金属层; 在所得结构的整个表面上顺序地形成绝缘层和多层抗蚀剂层，并且同时形成除了欧姆金属层以外的第一区域和不包括欧姆金属层的第二区域中具有不同形状的抗蚀剂图案，其中最下面 抗蚀剂图案在第一区域中暴露，并且绝缘层在第二区域中暴露; 通过分别使用抗蚀剂图案作为蚀刻掩模，同时蚀刻暴露的绝缘层和暴露的最下面的抗蚀剂图案来暴露衬底和绝缘层; 对曝光的衬底进行凹陷处理并蚀刻暴露的绝缘层以露出衬底; 以及在衬底上形成具有彼此不同蚀刻深度的栅极凹陷区域，沉积预定的栅极金属和去除抗蚀剂图案。 在该方法中，可以使用最少数量的工艺来制造具有不同阈值电压的晶体管，而不需要额外的掩模图案，结果可以降低生产成本，并且可以提高半导体器件的稳定性和生产率。

公开(公告)号：US20130069173A1

公开(公告)日：2013-03-21

申请号：US13592560

申请日：2012-08-23

Applicant: Woo Jin CHANG ,  Jong Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

Inventor： Woo Jin CHANG ,  Jong Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode;and a metal configured to connect the field plate and the source electrode.

Abstract translation: 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

公开(公告)号：US08248453B2

公开(公告)日：2012-08-21

申请号：US11975501

申请日：2007-10-19

Applicant: Jong Phil Lee ,  Woo Jin Chang

Inventor： Jong Phil Lee ,  Woo Jin Chang

IPC: H04N7/14

CPC classification number: H04W76/18 ,  H04W8/22

Abstract: A call control system and method for mobile video telephony that enables an automatic call setup between a mobile video telephony terminal and a mobile audio-dedicated terminal is disclosed. A call control method for communication between mobile terminals having different capabilities includes receiving, at a called party terminal, a call setup message, transmitting a disconnection message to a calling party terminal in response to the video call setup message and performing a call setup procedure triggered by the called part terminal.

Abstract translation: 公开了一种用于移动视频电话的呼叫控制系统和方法，其实现移动视频电话终端和移动音频专用终端之间的自动呼叫建立。 用于具有不同能力的移动终端之间的通信的呼叫控制方法包括在被叫方终端接收呼叫建立消息，响应于视频呼叫建立消息向呼叫方终端发送断开消息，并且执行呼叫建立过程触发 由被叫部分终端。

公开(公告)号：US07973368B2

公开(公告)日：2011-07-05

申请号：US12122982

申请日：2008-05-19

Applicant: Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

Inventor： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/778 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/66462

Abstract: Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.

Abstract translation: 提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。 在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部 在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。 因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

公开(公告)号：US20110086352A1

公开(公告)日：2011-04-14

申请号：US12888917

申请日：2010-09-23

Applicant: Rashid BASHIR ,  Yi-Shao LIU ,  Eric SALM ,  Woo-Jin CHANG

Inventor： Rashid BASHIR ,  Yi-Shao LIU ,  Eric SALM ,  Woo-Jin CHANG

IPC: C12Q1/68 ,  C12M1/34

CPC classification number: C12Q1/6825 ,  B01L3/0241 ,  B01L3/5027 ,  B01L3/502746 ,  B01L3/502761 ,  B01L3/502784 ,  B01L7/52 ,  B01L2200/0668 ,  B01L2200/10 ,  B01L2200/143 ,  B01L2200/147 ,  B01L2300/0645 ,  B01L2300/0681 ,  B01L2300/0867 ,  B01L2300/1822 ,  B01L2300/1827 ,  B01L2400/0418 ,  B01L2400/0424 ,  B01L2400/084 ,  B03C5/026

Abstract: Provided are methods and devices for label-free detection of nucleic acids that are amplified by polymerase chain reaction. A solution containing the components necessary for a PCR is introduced to a microfluidic amplification chamber and an electric field applied to a confined region in which PCR occurs. PCR product generated in the confined region is detected by measuring an electrical parameter that is, for example, solution impedance. The devices and methods provided herein are used, for example, in assays to detect one or more pathogens or for point-of-care tests. In an aspect, the PCR product is confined to droplets and the assay relates to detecting an electrical parameter of a flowing droplet, thereby detecting PCR product without a label. In an aspect, the PCR occurs in the droplet.

Abstract translation: 提供了通过聚合酶链反应扩增的用于无标记检测核酸的方法和装置。 将含有PCR所必需的成分的溶液引入微流体扩增室，并施加到发生PCR的限制区域的电场。 通过测量例如溶液阻抗的电参数来检测在限制区域中产生的PCR产物。 本文提供的装置和方法例如用于检测一种或多种病原体或用于点护理测试的测定中。 在一方面，PCR产物被限制在液滴中，并且该测定涉及检测流动液滴的电参数，从而检测没有标签的PCR产物。 在一方面，PCR在液滴中发生。

公开(公告)号：US07902572B2

公开(公告)日：2011-03-08

申请号：US12122805

申请日：2008-05-19

Applicant: Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

Inventor： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

IPC: H01L31/072

CPC classification number: H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

Abstract: A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract translation: 提供了具有头部比脚部宽的T形或/或G字形精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。