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公开(公告)号：US08779811B2
公开(公告)日：2014-07-15
申请号：US13196394
申请日：2011-08-02
申请人： Marco Passerini , Stefano Surico
发明人： Marco Passerini , Stefano Surico
摘要： Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.
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2.发明申请METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES 有权非线性电子设备编程过程中的程序脉冲发生方法与系统公开(公告)号：US20120106250A1
公开(公告)日：2012-05-03
申请号：US13346979
申请日：2012-01-10
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.
摘要翻译： 在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。 以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。 更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。
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公开(公告)号：US20080101133A1
公开(公告)日：2008-05-01
申请号：US11554797
申请日：2006-10-31
IPC分类号： G11C5/14
CPC分类号： G11C16/10 , G11C16/0483
摘要： A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
摘要翻译： 存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致 晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。
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4.发明授权Finite state machine interface has arbitration structure to store command generated by internal circuits during evaluation phase of state machine for FLASH EEPROM device 有权有限状态机接口具有仲裁结构，用于存储闪存EEPROM器件状态机评估阶段内部电路产生的指令公开(公告)号：US07284144B2
公开(公告)日：2007-10-16
申请号：US10309759
申请日：2002-12-04
申请人： Stefano Surico
发明人： Stefano Surico
IPC分类号： G06F1/04
CPC分类号： G05B19/045 , G05B2219/23245 , G05B2219/23289 , G11C16/06
摘要： An interface is provided for an integrated system that includes internal circuits, with each internal circuit functioning based upon its own clock. The interface includes a finite state machine for managing asynchronous and independent interactions between the internal circuits and external circuits. The finite state machine functions based upon a unique clock and a unique reset. The interface also includes an arbitration circuit connected to the finite state machine for receiving input signals for the finite state machine. The arbitration circuit includes a memory buffer for storing signals generated by the internal circuits when the finite state machine is performing an evaluation. The interface may be used to form a command interpreter of a non-volatile memory device.
摘要翻译： 为包括内部电路的集成系统提供了一个接口，每个内部电路基于其自己的时钟而起作用。 该接口包括用于管理内部电路和外部电路之间的异步和独立交互的有限状态机。 有限状态机基于独特的时钟和独特的复位功能。 接口还包括连接到有限状态机的仲裁电路，用于接收有限状态机的输入信号。 仲裁电路包括存储缓冲器，用于在有限状态机执行评估时存储由内部电路产生的信号。 该接口可以用于形成非易失性存储器件的命令解释器。
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公开(公告)号：US07249215B2
公开(公告)日：2007-07-24
申请号：US11635315
申请日：2006-12-07
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.
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6.发明授权Logic circuit for a semiconductor memory device, and method of managing an operation in the semiconductor memory device 失效用于半导体存储器件的逻辑电路，以及管理半导体存储器件中的操作的方法公开(公告)号：US08456917B1
公开(公告)日：2013-06-04
申请号：US13306741
申请日：2011-11-29
申请人： Stefano Surico , Giuseppe Moioli
发明人： Stefano Surico , Giuseppe Moioli
IPC分类号： G11C11/34 , H03K19/173
CPC分类号： G11C7/1063 , G11C16/10 , G11C16/32 , H03K19/17768
摘要： A logic circuit for a semiconductor memory device, includes a first logic portion which stores data from a first data signal, and generates a second data signal based on the first data signal, a second logic portion which generates a first address signal and stores an address from the first address signal where data from the second data signal is to be written, and a third logic portion which generates a flag signal which indicates whether the data stored in the first logic portion is valid.
摘要翻译： 一种用于半导体存储器件的逻辑电路，包括第一逻辑部分，其存储来自第一数据信号的数据，并且基于第一数据信号产生第二数据信号;第二逻辑部分，其生成第一地址信号并存储地址 从第二数据信号的数据写入的第一地址信号和产生指示第一逻辑部分中存储的数据是否有效的标志信号的第三逻辑部分。
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公开(公告)号：US07589572B2
公开(公告)日：2009-09-15
申请号：US11611416
申请日：2006-12-15
IPC分类号： H03L7/00
摘要： Apparatus, systems, and methods are disclosed that operate to trigger a reference voltage generator from a supply voltage detector, compare an output voltage level from the reference voltage generator with a supply voltage, and to generate an enable signal when the supply voltage is greater than the output voltage level. Additional apparatus, systems, and methods are disclosed.
摘要翻译： 公开了用于从电源电压检测器触发参考电压发生器的装置，系统和方法，将来自参考电压发生器的输出电压电平与电源电压进行比较，并且当电源电压大于 输出电压电平。 公开了附加装置，系统和方法。
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8.发明授权Implementation of column redundancy for a flash memory with a high write parallelism 有权实现具有高写入并行性的闪存的列冗余公开(公告)号：US07551498B2
公开(公告)日：2009-06-23
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译： 冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。 冗余地址寄存器存储有缺陷的常规存储单元的地址。 在n组r个锁存器中提供冗余锁存器。 冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。 如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。 所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。
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9.发明授权Apparatus and method to manage external voltage for semiconductor memory testing with serial interface 有权使用串行接口管理半导体存储器测试的外部电压的装置和方法公开(公告)号：US07525856B2
公开(公告)日：2009-04-28
申请号：US11696521
申请日：2007-04-04
IPC分类号： G11C29/00
CPC分类号： G11C29/32 , G11C29/003 , G11C29/1201
摘要： A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.
摘要翻译： 串行接口闪存设备包括数据/地址I / O引脚和时钟输入引脚。 双向缓冲器耦合到数据/地址I / O引脚。 包括数据方向控制的串行接口逻辑块耦合到时钟引脚，双向缓冲器，内部控制逻辑以及读取电压和修改电压发生器。 第一开关耦合到读电压发生器和时钟缓冲器，第二开关耦合到修改电压发生器和时钟缓冲器，第一和第二开关各自具有控制输入。 存储器驱动器通过第一和第二开关耦合到读取电压发生器和修改电压发生器。 第一和第二寄存器耦合在串行接口逻辑与第一和第二开关之间。 存储器阵列耦合到存储器驱动器和读取放大器，并且程序缓冲器耦合在串行接口逻辑和存储器驱动器之间。
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公开(公告)号：US20080310232A1
公开(公告)日：2008-12-18
申请号：US12194280
申请日：2008-08-19
CPC分类号： G11C16/344 , G11C16/0483
摘要： Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells, and second word lines configured to apply a second voltage to gates of the second memory cells during the verify operation.
摘要翻译： 各种实施例包括具有第一存储器单元的存储器件和方法以及以串排布置的第一存储器单元耦合的第二存储器单元，第一字线被配置为在第一存储器的验证操作期间向第一存储器单元的栅极施加第一电压 单元和第二字线，其被配置为在验证操作期间将第二电压施加到第二存储单元的栅极。
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