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公开(公告)号：US07864583B2
公开(公告)日：2011-01-04
申请号：US12194280
申请日：2008-08-19
IPC分类号： G11C16/00
CPC分类号： G11C16/344 , G11C16/0483
摘要： Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells, and second word lines configured to apply a second voltage to gates of the second memory cells during the verify operation.
摘要翻译： 各种实施例包括具有第一存储器单元的存储器件和方法以及以串排布置的第一存储器单元耦合的第二存储器单元，第一字线被配置为在第一存储器的验证操作期间向第一存储器单元的栅极施加第一电压 单元和第二字线，其被配置为在验证操作期间将第二电压施加到第二存储单元的栅极。
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公开(公告)号：US08779811B2
公开(公告)日：2014-07-15
申请号：US13196394
申请日：2011-08-02
申请人： Marco Passerini , Stefano Surico
发明人： Marco Passerini , Stefano Surico
摘要： Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.
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3.发明申请FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY 有权灵活，低成本的设备和方法来引导和检查非易失性存储器中的算法修改公开(公告)号：US20080250191A1
公开(公告)日：2008-10-09
申请号：US11696288
申请日：2007-04-04
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
摘要翻译： 闪速存储器包括输入/输出缓冲器，具有耦合到输入/输出缓冲器的存储器单元的存储器阵列以及行和列解码器，以及耦合到行和列解码器的电压发生器电路。 微控制器耦合到命令用户界面。 开关指令电路在命令用户界面的控制下，从只读存储器和从芯片到板上t锁存器选择性地向微控制器提供指令，耦合到输入/输出缓冲器。
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公开(公告)号：US20080165585A1
公开(公告)日：2008-07-10
申请号：US11619978
申请日：2007-01-04
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。 通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作 所选单位。 通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作 。 验证奇数和偶数字线可以以任何顺序执行。
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5.发明授权Apparatus and method to manage external voltage for semiconductor memory testing with serial interface 有权使用串行接口管理半导体存储器测试的外部电压的装置和方法公开(公告)号：US07525856B2
公开(公告)日：2009-04-28
申请号：US11696521
申请日：2007-04-04
IPC分类号： G11C29/00
CPC分类号： G11C29/32 , G11C29/003 , G11C29/1201
摘要： A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.
摘要翻译： 串行接口闪存设备包括数据/地址I / O引脚和时钟输入引脚。 双向缓冲器耦合到数据/地址I / O引脚。 包括数据方向控制的串行接口逻辑块耦合到时钟引脚，双向缓冲器，内部控制逻辑以及读取电压和修改电压发生器。 第一开关耦合到读电压发生器和时钟缓冲器，第二开关耦合到修改电压发生器和时钟缓冲器，第一和第二开关各自具有控制输入。 存储器驱动器通过第一和第二开关耦合到读取电压发生器和修改电压发生器。 第一和第二寄存器耦合在串行接口逻辑与第一和第二开关之间。 存储器阵列耦合到存储器驱动器和读取放大器，并且程序缓冲器耦合在串行接口逻辑和存储器驱动器之间。
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公开(公告)号：US20080310232A1
公开(公告)日：2008-12-18
申请号：US12194280
申请日：2008-08-19
CPC分类号： G11C16/344 , G11C16/0483
摘要： Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells, and second word lines configured to apply a second voltage to gates of the second memory cells during the verify operation.
摘要翻译： 各种实施例包括具有第一存储器单元的存储器件和方法以及以串排布置的第一存储器单元耦合的第二存储器单元，第一字线被配置为在第一存储器的验证操作期间向第一存储器单元的栅极施加第一电压 单元和第二字线，其被配置为在验证操作期间将第二电压施加到第二存储单元的栅极。
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7.发明申请APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR MEMORY TESTING WITH SERIAL INTERFACE 有权用于串行接口的半导体存储器测试管理外部电压的装置和方法公开(公告)号：US20080246504A1
公开(公告)日：2008-10-09
申请号：US11696521
申请日：2007-04-04
IPC分类号： G01R31/00
CPC分类号： G11C29/32 , G11C29/003 , G11C29/1201
摘要： A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.
摘要翻译： 串行接口闪存设备包括数据/地址I / O引脚和时钟输入引脚。 双向缓冲器耦合到数据/地址I / O引脚。 包括数据方向控制的串行接口逻辑块耦合到时钟引脚，双向缓冲器，内部控制逻辑以及读取电压和修改电压发生器。 第一开关耦合到读电压发生器和时钟缓冲器，第二开关耦合到修改电压发生器和时钟缓冲器，第一和第二开关各自具有控制输入。 存储器驱动器通过第一和第二开关耦合到读取电压发生器和修改电压发生器。 第一和第二寄存器耦合在串行接口逻辑与第一和第二开关之间。 存储器阵列耦合到存储器驱动器和读取放大器，并且程序缓冲器耦合在串行接口逻辑和存储器驱动器之间。
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公开(公告)号：US08884666B2
公开(公告)日：2014-11-11
申请号：US13196394
申请日：2011-08-02
申请人： Marco Passerini , Stefano Surico
发明人： Marco Passerini , Stefano Surico
CPC分类号： G11C29/028 , G06F1/06 , G11C7/04 , G11C7/222 , G11C29/023 , G11C29/12015 , H03K3/0231
摘要： Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.
摘要翻译： 本文公开了一种装置，包括用于第一时钟信号的第一端子，与第一时钟信号基本互补的第二时钟信号的第二端子，第三时钟信号的第三端子，与第四时钟信号基本互补的第四端子 到第三时钟信号，产生第一中间信号的第一逻辑门，产生第二中间信号的第二逻辑门，产生第三中间信号的第一延迟电路和产生第四中间信号的第二延迟电路 以及耦合到第一和第二延迟电路以分别在第三和第四端子处产生第三和第四时钟信号的第一输出电路。
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公开(公告)号：US20130033947A1
公开(公告)日：2013-02-07
申请号：US13196394
申请日：2011-08-02
申请人： Marco Passerini , Stefano Surico
发明人： Marco Passerini , Stefano Surico
CPC分类号： G11C29/028 , G06F1/06 , G11C7/04 , G11C7/222 , G11C29/023 , G11C29/12015 , H03K3/0231
摘要： Disclosed herein is a clock generator that comprises a master or first oscillator having an output terminal which provides a master clock signal and at least one slave or second oscillator having an output terminal which provides a slave clock signal, the master and slave oscillators comprising respective time delay stages and latches, the slave oscillator also comprising logic gates connected to the outputs of the latches and configured to logically combine said outputs to generate a slave clock signal having a different phase with respect to a master clock signal.
摘要翻译： 这里公开了一种时钟发生器，其包括具有提供主时钟信号的输出端子的主器件或第一振荡器以及具有提供从时钟信号的输出端子的至少一个从器件或第二振荡器，所述主器件和从器件振荡器包括相应的时间 延迟级和锁存器，从属振荡器还包括连接到锁存器的输出的逻辑门，并且被配置为逻辑地组合所述输出以产生相对于主时钟信号具有不同相位的从时钟信号。
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10.发明授权Flexible, low cost apparatus and method to introduce and check algorithm modifications in a non-volatile memory 有权灵活，低成本的装置和方法来引入和检查非易失性存储器中的算法修改公开(公告)号：US07769943B2
公开(公告)日：2010-08-03
申请号：US11696288
申请日：2007-04-04
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
摘要翻译： 闪速存储器包括输入/输出缓冲器，具有耦合到输入/输出缓冲器的存储器单元的存储器阵列以及行和列解码器，以及耦合到行和列解码器的电压发生器电路。 微控制器耦合到命令用户界面。 开关指令电路在命令用户界面的控制下，从只读存储器和从芯片到板上t锁存器选择性地向微控制器提供指令，耦合到输入/输出缓冲器。
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