公开(公告)号：US5237694A

公开(公告)日：1993-08-17

申请号：US707855

申请日：1991-05-30

申请人： Stephen P. Horne ,  Seungyoon Song

发明人： Stephen P. Horne ,  Seungyoon Song

IPC分类号： G06F9/46 ,  G06F15/167

CPC分类号： G06F9/52 ,  G06F15/167

摘要： There is described a system and method for use in a processing system of the type including a plurality of processor subsystems, each processor subsystem including a processor, and being coupled together and to a shared memory by a common bus, wherein the system and method permits exclusive execution of critical sections by each of the processors. A lock buffer associated with each of the processors caches the value of the interlock variable and a control section locally tests the stored interlock variable value responsive to an instruction from its processor. If the control section determines that the interlock variable has the available value, it causes the available value of the interlock variable to be conveyed to its associated processor and the busy value to be written to the local lock buffer and over the common bus to the shared memory under a write-through policy and for updating each lock buffer associated with the other processors under a write-update policy. When its processor completes its critical section, the control section causes the available value of the interlock variable to be written to the local lock buffer and over the common bus to the shared memory so that the other lock buffers update their stored values of the interlock variable to the available value.

摘要翻译： 描述了在包括多个处理器子系统的处理系统中使用的系统和方法，每个处理器子系统包括处理器，并且通过公共总线耦合在一起并且共享存储器，其中系统和方法允许 由每个处理器独占执行关键部分。 与每个处理器相关联的锁定缓冲器缓存互锁变量的值，并且控制部分响应于来自其处理器的指令来本地测试存储的互锁变量值。 如果控制部分确定互锁变量具有可用值，则会使互锁变量的可用值传送到其关联的处理器，并将忙值写入本地锁缓冲区，并将公共总线写入共享 存储器，并根据写更新策略更新与其他处理器相关联的每个锁定缓冲区。 当其处理器完成关键部分时，控制部分将互锁变量的可用值写入本地锁定缓冲器，并通过公共总线写入共享存储器，以便其他锁定缓冲器更新其互锁变量的存储值 到可用值。

公开(公告)号：US20070214323A1

公开(公告)日：2007-09-13

申请号：US11559133

申请日：2006-11-13

申请人： Laurent Moll ,  Seungyoon Song ,  Peter Glaskowsky ,  Yu Cheng

发明人： Laurent Moll ,  Seungyoon Song ,  Peter Glaskowsky ,  Yu Cheng

IPC分类号： G06F13/28

CPC分类号： G06F12/0802 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0875 ,  G06F12/0888 ,  G06F13/1694 ,  G06F2212/1028 ,  G06F2212/2515 ,  Y02D10/13 ,  Y02D10/14

摘要： Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format metal layer on the second electrically

摘要翻译： 通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。 在缓冲模式下，当CPU开始在低功耗状态下运行时，与缓存/微型缓存进行匹配的非缓存访问（例如由DMA设备产生的）与指定的物理地址范围匹配，而不是由存储器控制器 和DRAM。 缓冲/微型缓存处理包括在引用未命中时分配线路，以及当引用命中时从缓冲器/微型缓存器返回缓存数据。 根据多个替换策略中的一个替换策略，在缓冲器/微型缓存中替换行，包括当没有可用的空行时停止替换。 在正常模式下，当CPU开始在高功率状态下运行时，缓冲器/微型缓存类似于常规高速缓存，并且不能处理非缓存访问。 在一个使用场景中，保留在缓冲/微型缓存中的数据是第二次电压维持在压缩格式金属层中的图形刷新数据

公开(公告)号：US20070113015A1

公开(公告)日：2007-05-17

申请号：US11351070

申请日：2006-02-09

申请人： Laurent Moll ,  Seungyoon Song ,  Peter Glaskowsky ,  Yu Cheng

发明人： Laurent Moll ,  Seungyoon Song ,  Peter Glaskowsky ,  Yu Cheng

IPC分类号： G06F12/00

CPC分类号： G06F12/0802 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0875 ,  G06F12/0888 ,  G06F13/1694 ,  G06F2212/1028 ,  G06F2212/2515 ,  Y02D10/13 ,  Y02D10/14

摘要： Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.

摘要翻译： 通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。 在缓冲模式下，当CPU开始在低功耗状态下运行时，与缓存/微型缓存进行匹配的非缓存访问（例如由DMA设备产生的）与指定的物理地址范围匹配，而不是由存储器控制器 和DRAM。 缓冲/微型缓存处理包括在引用未命中时分配线路，以及当引用命中时从缓冲器/微型缓存器返回缓存数据。 根据多个替换策略中的一个替换策略，在缓冲器/微型缓存中替换行，包括当没有可用的空行时停止替换。 在正常模式下，当CPU开始在高功率状态下运行时，缓冲器/微型缓存类似于常规高速缓存，并且不能处理非缓存访问。 在一种使用场景中，保留在缓冲/微型缓存中的数据是以压缩格式维护的图形刷新数据。

公开(公告)号：US20070186057A1

公开(公告)日：2007-08-09

申请号：US11559069

申请日：2006-11-13

申请人： Laurent MOLL ,  Yu CHENG ,  Peter GLASKOWSKY ,  Seungyoon SONG

发明人： Laurent MOLL ,  Yu CHENG ,  Peter GLASKOWSKY ,  Seungyoon SONG

IPC分类号： G06F13/28

CPC分类号： G06F12/0835 ,  G06F1/3225 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/0888 ,  G06F2212/1028 ,  G06F2212/6046 ,  Y02D10/13

摘要： Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).

摘要翻译： 当微处理器中的缓存数据由于任何或所有微处理器处于低电平状态时，微处理器中的高速缓存数据不可访问时，小型和功率高效的缓冲器/微型高速缓冲存储器源和接收器被选择指向微处理器的相干域中的存储器空间， 电源状态不支持窥探。 通过缓冲器/微型缓存来满足所选择的DMA访问通过允许微处理器（或其一部分）保持在低功率状态来降低功耗。 缓冲器/微型高速缓存可以相对于微处理器中的高速缓存数据非相干地操作（暂时地），并且在微处理器（或其部分）转换到启用窥探的高功率状态之前，在去激活之前刷新以与缓存数据同步 。 或者，缓冲器/微型缓存可以以与缓存的数据相一致的方式（递增地）操作。 微处理器实现具有相关联的高速缓存系统（例如第一，第二和更高级别高速缓存的各种布置）的一个或多个处理器。

公开(公告)号：US20070130382A1

公开(公告)日：2007-06-07

申请号：US11351058

申请日：2006-02-09

申请人： Laurent Moll ,  Yu Cheng ,  Peter Glaskowsky ,  Seungyoon Song

发明人： Laurent Moll ,  Yu Cheng ,  Peter Glaskowsky ,  Seungyoon Song

IPC分类号： G06F13/28

CPC分类号： G06F12/0835 ,  G06F12/0875 ,  G06F13/28 ,  G06F2212/1028 ,  Y02D10/13

摘要： A small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).

摘要翻译： 当微处理器中的高速缓存数据由于微处理器中的任何一个或全部处于低电平状态而无法访问时，小型和功率高效的缓冲器/微型缓存器将选择的DMA访问定向到微处理器的相干域中的存储器空间 电源状态不支持窥探。 通过缓冲器/微型缓存来满足所选择的DMA访问通过允许微处理器（或其一部分）保持在低功率状态来降低功耗。 缓冲器/微型高速缓存可以相对于微处理器中的高速缓存数据非相干地操作（暂时地），并且在微处理器（或其部分）转换到启用窥探的高功率状态之前，在去激活之前刷新以与缓存的数据同步 。 或者，缓冲器/微型缓存可以以与缓存的数据相一致的方式（递增地）操作。 微处理器实现具有相关联的高速缓存系统（例如第一，第二和更高级别高速缓存的各种布置）的一个或多个处理器。