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    Method and apparatus for safely dechucking wafers
    1.
    发明授权
    Method and apparatus for safely dechucking wafers 有权
    用于安全地脱扣晶片的方法和装置

    公开(公告)号：US08000081B2

    公开(公告)日：2011-08-16

    申请号：US12172642

    申请日：2008-07-14

    Applicant: Chung-Tsung Lu ,  Pin-Chia Su ,  Yu-Chih Liou

    Inventor： Chung-Tsung Lu ,  Pin-Chia Su ,  Yu-Chih Liou

    IPC: H01L21/683 ,  H01T23/00

    CPC classification number: H01L21/6833

    Abstract: A wafer stage installed in a process chamber for safely dechucking a wafer is provided. In one embodiment, the wafer stage comprises: a chuck support for supporting a chuck; a chuck mounted on the chuck support for receiving and attaching a wafer thereto; a support lift means for supporting the wafer; a driving means coupled to the support lift means for gradually raising the support lift means to contact the wafer in response to a variable quantity; a sensor attached to the driving means for detecting a change in the variable quantity; and a controller for controlling the variable quantity to the driving means when a predetermined variable quantity is detected in comparison to the change in the variable quantity for a predetermined time.

    Abstract translation: 提供了安装在用于安全地脱扣晶片的处理室中的晶片台。 在一个实施例中，晶片台包括：用于支撑卡盘的卡盘支撑件; 安装在卡盘支架上的用于接收和附接晶片的卡盘; 用于支撑晶片的支撑提升装置; 连接到所述支撑提升装置的驱动装置，用于逐渐升高所述支撑提升装置以响应于可变量与所述晶片接触; 附接到驱动装置的传感器，用于检测可变量的变化; 以及控制器，用于当与预定时间内的可变量的变化相比较检测到预定可变量时，控制对驱动装置的可变量。

    SILICON WAFER RECLAMATION PROCESS
    2.
    发明申请
    SILICON WAFER RECLAMATION PROCESS 有权
    硅胶回收工艺

    公开(公告)号：US20110062375A1

    公开(公告)日：2011-03-17

    申请号：US12952540

    申请日：2010-11-23

    Applicant: Tai-Yung Yu ,  Yu-Sheng Su ,  Li-Te Hsu ,  Jin-Lin Liang ,  Pin-Chia Su

    Inventor： Tai-Yung Yu ,  Yu-Sheng Su ,  Li-Te Hsu ,  Jin-Lin Liang ,  Pin-Chia Su

    IPC: C09K13/08

    CPC classification number: H01L21/02032 ,  H01L21/31111

    Abstract: An etchant for removing a porous low-k dielectric layer on a semiconductor substrate includes a hydrofluoric acid-based solvent, a dilating additive for dilating the pores in the porous low-k dielectric, and a passivating additive that forms a passivation layer at the interface between the low-k dielectric layer and the semiconductor substrate.

    Abstract translation: 用于去除半导体衬底上的多孔低k电介质层的蚀刻剂包括氢氟酸溶剂，用于膨胀多孔低k电介质中的孔的扩张添加剂和在界面处形成钝化层的钝化添加剂 在低k电介质层和半导体衬底之间。

    SILICON WAFER RECLAMATION PROCESS
    4.
    发明申请
    SILICON WAFER RECLAMATION PROCESS 有权
    硅胶回收工艺

    公开(公告)号：US20090111269A1

    公开(公告)日：2009-04-30

    申请号：US11931796

    申请日：2007-10-31

    Applicant: Tai-Yung Yu ,  Yu-Sheng Su ,  Li-Te Hsu ,  Jin-Lin Liang ,  Pin-Chia Su

    Inventor： Tai-Yung Yu ,  Yu-Sheng Su ,  Li-Te Hsu ,  Jin-Lin Liang ,  Pin-Chia Su

    IPC: H01L21/311 ,  C09K13/08

    CPC classification number: H01L21/02032 ,  H01L21/31111

    Abstract: By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.

    Abstract translation: 通过在包含扩张添加剂和钝化添加剂的基于HF的低k电介质蚀刻溶剂中暴露其上具有多孔低k电介质层的工艺控制晶片，低k电介质层中的孔被扩大其中一些 彼此连接以形成延伸穿过介电层厚度的一个或多个连续通道，并允许基于HF的溶剂到达基底。 然后，基于HF的蚀刻溶剂的钝化添加剂组分在介电层和衬底界面处形成钝化层，保护衬底免受基于HF的蚀刻剂的影响。

    Method for protecting a wafer backside from etching damage
    5.
    发明授权
    Method for protecting a wafer backside from etching damage 有权
    用于保护晶片背面免受蚀刻损伤的方法

    公开(公告)号：US06777334B2

    公开(公告)日：2004-08-17

    申请号：US10190073

    申请日：2002-07-03

    Applicant: Le Der Shiu ,  Pin Chia Su ,  Yin Shen Chu

    Inventor： Le Der Shiu ,  Pin Chia Su ,  Yin Shen Chu

    IPC: H01L21461

    CPC classification number: H01L21/02071 ,  H01L21/02052 ,  H01L21/31116

    Abstract: A method for protecting a silicon semiconductor wafer backside surface for removing polymer containing residues from a wafer process surface including providing a silicon semiconductor wafer having a process surface and a backside surface said process surface including metal containing features said process surface at least partially covered with polymer containing residues and said backside surface including exposed silicon containing areas; forming an etching resistant oxide layer over the exposed silicon containing areas; and, subjecting the silicon semiconductor wafer to a series of cleaning steps including a wet etchant corrosive to the exposed silicon containing areas.

    Abstract translation: 一种用于保护硅半导体晶片背面的方法，用于从晶片工艺表面除去含有残留物的聚合物，包括提供具有工艺表面和背面的硅半导体晶片，所述工艺表面包括含有金属的特征，所述工艺表面至少部分地被聚合物覆盖 含有残留物和所述背面包括暴露的含硅区域; 在暴露的含硅区域上形成耐蚀刻氧化物层; 并且对硅半导体晶片进行一系列清洁步骤，包括对暴露的含硅区域具有腐蚀性的湿蚀刻剂。

    System for securely dechucking wafers
    6.
    发明授权
    System for securely dechucking wafers 有权
    用于安全地脱扣晶片的系统

    公开(公告)号：US08416555B2

    公开(公告)日：2013-04-09

    申请号：US13189984

    申请日：2011-07-25

    Applicant: Chung-Tsung Lu ,  Pin-Chia Su ,  Yu-Chih Liou

    Inventor： Chung-Tsung Lu ,  Pin-Chia Su ,  Yu-Chih Liou

    IPC: H01L21/683 ,  H01T23/00

    CPC classification number: H01L21/6833

    Abstract: A system for chucking and de-chucking a work piece comprises a wafer stage having a chuck support for supporting a chuck. The wafer stage further comprises a chuck mounted on the chuck support for receiving and attaching the work piece thereto; a support lift means for supporting the work piece; a driving means coupled to the support lift means for gradually raising the support lift means to contact the work piece in response to a variable quantity; a controller for receiving the variable quantity; and a regulating means coupled to the driving means and to the controller, the regulating means for controlling the variable quantity going to the driving means when a predetermined variable quantity is detected.

    Abstract translation: 用于夹紧和去夹紧工件的系统包括具有用于支撑卡盘的卡盘支撑件的晶片台。 晶片台还包括安装在卡盘支架上的卡盘，用于接收和附接工件; 用于支撑工件的支撑提升装置; 驱动装置，联接到所述支撑提升装置，用于逐渐升高所述支撑提升装置，以响应于可变量接触所述工件; 用于接收可变量的控制器; 以及调节装置，其耦合到所述驱动装置和所述控制器，所述调节装置用于当检测到预定可变量时控制进入所述驱动装置的可变量。

    Silicon wafer reclamation process
    8.
    发明授权
    Silicon wafer reclamation process 有权
    硅片回收工艺

    公开(公告)号：US07851374B2

    公开(公告)日：2010-12-14

    申请号：US11931796

    申请日：2007-10-31

    Applicant: Tai-Yung Yu ,  Yu-Sheng Su ,  Li-Te Hsu ,  Jin-Lin Liang ,  Pin-Chia Su

    Inventor： Tai-Yung Yu ,  Yu-Sheng Su ,  Li-Te Hsu ,  Jin-Lin Liang ,  Pin-Chia Su

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/02032 ,  H01L21/31111

    Abstract: By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.

    Abstract translation: 通过在包含扩张添加剂和钝化添加剂的基于HF的低k电介质蚀刻溶剂中暴露其上具有多孔低k电介质层的工艺控制晶片，低k电介质层中的孔被扩大其中一些 彼此连接以形成延伸穿过介电层厚度的一个或多个连续通道，并允许基于HF的溶剂到达基底。 然后，基于HF的蚀刻溶剂的钝化添加剂组分在介电层和衬底界面处形成钝化层，保护衬底免受基于HF的蚀刻剂的影响。

    Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices
    10.
    发明申请
    Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices 有权
    整合浅结N沟道器件的形成与形成P沟道，ESD和输入/输出器件的方法

    公开(公告)号：US20050191802A1

    公开(公告)日：2005-09-01

    申请号：US10788170

    申请日：2004-02-26

    Applicant: Yu-Lung Yeh ,  Chu-We Hu ,  Li-Te Hsu ,  Pin-Chia Su

    Inventor： Yu-Lung Yeh ,  Chu-We Hu ,  Li-Te Hsu ,  Pin-Chia Su

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02

    CPC classification number: H01L21/823814 ,  H01L27/0266

    Abstract: The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region. The flow of CF4 in the plasma tool during the photoresist removing plasma ashing procedure, as well as the length of the post-plasma ashing wet clean procedure, have both been reduced resulting in reduced exposure of the shallow source/drain region to these procedures.

    Abstract translation: 已经开发了制造具有浅源极/漏极区域的NMOS器件，其作为用于将其他类型器件的制造与NMOS器件的制造集成的集成工艺序列的一部分进行。 集成过程序列的关键特征是在形成其它类型器件之后形成NMOS的浅源/漏区，从而降低了浅源/漏区暴露于用于 其他类型的设备。 此外，用于去除用于保护完成的其它类型器件免于浅源/漏离子注入过程的光致抗蚀剂形状的方法已被再次修改，以减少对浅源/漏区的可能损坏。 在光致抗蚀剂去除等离子体灰化过程期间等离子体工具中的CF 4的流动以及后等离子体灰化湿法清洁程序的长度都被减少，导致浅的 源/漏区到这些程序。

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