知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

3 records (took 0.011 seconds)

    Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices
    1.
    发明授权
    Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices 有权
    整合浅结N沟道器件的形成与形成P沟道，ESD和输入/输出器件的方法

    公开(公告)号：US07101748B2

    公开(公告)日：2006-09-05

    申请号：US10788170

    申请日：2004-02-26

    Applicant: Yu-Lung Yeh ,  Chu-We Hu ,  Li-Te Hsu ,  Pin-Chia Su

    Inventor： Yu-Lung Yeh ,  Chu-We Hu ,  Li-Te Hsu ,  Pin-Chia Su

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L27/0266

    Abstract: The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region. The flow of CF4 in the plasma tool during the photoresist removing plasma ashing procedure, as well as the length of the post-plasma ashing wet clean procedure, have both been reduced resulting in reduced exposure of the shallow source/drain region to these procedures.

    Abstract translation: 已经开发了制造具有浅源极/漏极区域的NMOS器件，其作为用于将其他类型器件的制造与NMOS器件的制造集成的集成工艺序列的一部分进行。 集成过程序列的关键特征是在形成其它类型器件之后形成NMOS的浅源/漏区，从而降低了浅源/漏区暴露于用于 其他类型的设备。 此外，用于去除用于保护完成的其它类型器件免于浅源/漏离子注入过程的光致抗蚀剂形状的方法已被再次修改，以减少对浅源/漏区的可能损坏。 在光致抗蚀剂去除等离子体灰化过程期间等离子体工具中的CF 4的流动以及后等离子体灰化湿法清洁程序的长度都被减少，导致浅的 源/漏区到这些程序。

    Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices
    2.
    发明申请
    Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices 有权
    整合浅结N沟道器件的形成与形成P沟道，ESD和输入/输出器件的方法

    公开(公告)号：US20050191802A1

    公开(公告)日：2005-09-01

    申请号：US10788170

    申请日：2004-02-26

    Applicant: Yu-Lung Yeh ,  Chu-We Hu ,  Li-Te Hsu ,  Pin-Chia Su

    Inventor： Yu-Lung Yeh ,  Chu-We Hu ,  Li-Te Hsu ,  Pin-Chia Su

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02

    CPC classification number: H01L21/823814 ,  H01L27/0266

    Abstract: The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region. The flow of CF4 in the plasma tool during the photoresist removing plasma ashing procedure, as well as the length of the post-plasma ashing wet clean procedure, have both been reduced resulting in reduced exposure of the shallow source/drain region to these procedures.

    Abstract translation: 已经开发了制造具有浅源极/漏极区域的NMOS器件，其作为用于将其他类型器件的制造与NMOS器件的制造集成的集成工艺序列的一部分进行。 集成过程序列的关键特征是在形成其它类型器件之后形成NMOS的浅源/漏区，从而降低了浅源/漏区暴露于用于 其他类型的设备。 此外，用于去除用于保护完成的其它类型器件免于浅源/漏离子注入过程的光致抗蚀剂形状的方法已被再次修改，以减少对浅源/漏区的可能损坏。 在光致抗蚀剂去除等离子体灰化过程期间等离子体工具中的CF 4的流动以及后等离子体灰化湿法清洁程序的长度都被减少，导致浅的 源/漏区到这些程序。

Patent Agency Ranking