公开(公告)号：US07655994B2

公开(公告)日：2010-02-02

申请号：US11259644

申请日：2005-10-26

申请人： Eduard A. Cartier ,  Mathew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

发明人： Eduard A. Cartier ,  Mathew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

IPC分类号： H01L29/94 ,  H01L21/326

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

公开(公告)号：US07566938B2

公开(公告)日：2009-07-28

申请号：US11281032

申请日：2005-11-17

申请人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L29/76

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

摘要翻译： 提供了一种制造氧化铪和/或氧化锆膜的方法。 所述方法包括提供溶解，乳化或悬浮在液体中的Hf和/或Zr醇盐的混合物; 至少蒸发醇盐并在大于400℃的温度下沉积蒸发的组分。所​​得膜是致密的，微晶的，并且当在氢等离子体中处理或形成气体退火时能够自钝化。

公开(公告)号：US06573197B2

公开(公告)日：2003-06-03

申请号：US09833550

申请日：2001-04-12

申请人： Alessandro C. Callegari ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey

发明人： Alessandro C. Callegari ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey

IPC分类号： H01L2131

CPC分类号： H01L21/02304 ,  C23C16/24 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02197 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/28035 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/31604 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention provides a method of fabricating a thermally stable polysilicon/high-k dielectric film stack utilizing a deposition method wherein Si-containing precursor gas which includes silicon and hydrogen is diluted with an inert gas such as He so as to significantly reduce the hydrogen content in the resultant polysilicon film. Semiconductor structures such as field effect transistors (FETs) and capacitors which include at least the thermally stable polysilicon/high-k dielectric film stack are also provided herein.

公开(公告)号：US06348419B1

公开(公告)日：2002-02-19

申请号：US09375763

申请日：1999-08-18

申请人： Frank Grellner ,  Paul C. Jamison ,  Glen L. Miles ,  David C. Mosher ,  Emmanuel Batt

发明人： Frank Grellner ,  Paul C. Jamison ,  Glen L. Miles ,  David C. Mosher ,  Emmanuel Batt

IPC分类号： H01L21302

CPC分类号： H01L22/26 ,  H01L21/3185

摘要： A method for adjusting an etch rate of a nitride layer, in accordance with the present invention includes, in a reaction chamber, providing a surface for depositing a nitride layer. The nitride layer is deposited on the surface by adjusting processing parameters to control an etch rate achievable for the nitride layer. The etch rate achievable results from the depositing step such that an ability to etch the nitride layer is determined by the adjustment of the process parameters. A refractive index measurement may be provided for monitoring the achievable etch rate for the nitride layer.

摘要翻译： 根据本发明的用于调整氮化物层的蚀刻速率的方法包括在反应室中提供用于沉积氮化物层的表面。 通过调整处理参数来将氮化物层沉积在表面上，以控制氮化物层可达到的蚀刻速率。 可以通过沉积步骤得到的蚀刻速率由蚀刻氮化物层的能力由工艺参数的调整决定。 可以提供折射率测量用于监测氮化物层的可实现的蚀刻速率。

公开(公告)号：US09059314B2

公开(公告)日：2015-06-16

申请号：US13602118

申请日：2012-09-01

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US08304836B2

公开(公告)日：2012-11-06

申请号：US12620234

申请日：2009-11-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US20110115027A1

公开(公告)日：2011-05-19

申请号：US12620234

申请日：2009-11-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/263

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US07858500B2

公开(公告)日：2010-12-28

申请号：US12062972

申请日：2008-04-04

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

IPC分类号： H01L21/479

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

摘要翻译： 一种半导体结构，特别是pFET，其包括具有大于SiO 2的介电常数和大于50％的Ge或Si含量的介电材料和至少一种用于通过材料堆的阈值/平带电压调谐的其它装置 提供工程。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：US07169674B2

公开(公告)日：2007-01-30

申请号：US11066762

申请日：2005-02-28

申请人： Nestor Alexander Bojarczuk, Jr. ,  Kevin Kok Chan ,  Christopher Peter D'Emic ,  Evgeni Gousev ,  Supratik Guha ,  Paul C. Jamison ,  Lars-Ake Ragnarsson

发明人： Nestor Alexander Bojarczuk, Jr. ,  Kevin Kok Chan ,  Christopher Peter D'Emic ,  Evgeni Gousev ,  Supratik Guha ,  Paul C. Jamison ,  Lars-Ake Ragnarsson

IPC分类号： H01L21/8236 ,  H01L21/8222 ,  H01L21/335 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/331

CPC分类号： H01L29/513 ,  H01L21/28194

摘要： A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.

摘要翻译： 用于具有沟道区和栅电极的场效应晶体管的扩散势垒（和形成扩散势垒的方法）包括设置在沟道区上的绝缘材料。 绝缘材料包括氮（N），并且设置在栅电极下方。 绝缘材料可以设置为层或分布在设置在栅电极下方的栅极电介质材料内。

公开(公告)号：US07115959B2

公开(公告)日：2006-10-03

申请号：US10873733

申请日：2004-06-22

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evengi Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph P. Shepard, Jr. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evengi Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph P. Shepard, Jr. ,  Sufi Zafar

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.