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    DOMINO LOGIC CIRCUIT AND PIPELINED DOMINO LOGIC CIRCUIT
    1.
    发明申请
    DOMINO LOGIC CIRCUIT AND PIPELINED DOMINO LOGIC CIRCUIT 有权
    多米尼加逻辑电路和管道多米诺逻辑电路

    公开(公告)号：US20090230994A1

    公开(公告)日：2009-09-17

    申请号：US12381360

    申请日：2009-03-11

    申请人： Young-Chul Rhee ,  Byung-Koan Kim ,  Ock-Chul Shin

    发明人： Young-Chul Rhee ,  Byung-Koan Kim ,  Ock-Chul Shin

    IPC分类号： H03K19/096 ,  H03K19/00

    CPC分类号： H03K19/0963

    摘要： A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

    摘要翻译： 多米诺逻辑电路包括输入电路和输出电路。 输入电路在时钟信号的第一阶段预充电动态节点。 输入电路通过在时钟信号的第二阶段执行输入数据的逻辑评估来确定动态节点的逻辑电平。 输出电路耦合在输出节点和动态节点之间。 输出电路响应于时钟信号和动态节点的逻辑电平来确定输出节点的逻辑电平。 当执行逻辑评估时，输出电路维持输出节点的逻辑电平。

    Skew adjustment circuit and a method thereof
    2.
    发明授权
    Skew adjustment circuit and a method thereof 有权
    倾斜调整电路及其方法

    公开(公告)号：US08139014B2

    公开(公告)日：2012-03-20

    申请号：US12247713

    申请日：2008-10-08

    申请人： Byung-koan Kim ,  Ock-chul Shin ,  Young-chul Rhee

    发明人： Byung-koan Kim ,  Ock-chul Shin ,  Young-chul Rhee

    IPC分类号： G09G3/36

    CPC分类号： H04L25/14 ,  H04L7/0008 ,  H04L7/0037

    摘要： Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.

    摘要翻译： 提供了一种偏斜调整电路及其方法。 偏斜调整电路输入输入时钟信号和输入起始脉冲信号，输出根据偏斜控制信号的偏斜值延迟的输出时钟信号和输出起始脉冲信号。 偏斜调整电路包括延迟电路，选择电路和输出电路。 响应于偏斜控制信号，延迟电路使输入时钟信号延迟偏斜值以产生输出时钟信号。 选择电路比较偏斜控制信号和偏移控制信号，以选择输入起始脉冲信号和延迟起始脉冲信号之一，以输出所选择的信号作为起始脉冲信号。 输出电路响应输出时钟信号，输出起始脉冲信号作为输出起始脉冲信号。

    Domino logic circuit and pipelined domino logic circuit
    3.
    发明授权
    Domino logic circuit and pipelined domino logic circuit 有权
    多米诺逻辑电路和流水线多米诺逻辑电路

    公开(公告)号：US07852121B2

    公开(公告)日：2010-12-14

    申请号：US12381360

    申请日：2009-03-11

    申请人： Young-Chul Rhee ,  Byung-Koan Kim ,  Ock-Chul Shin

    发明人： Young-Chul Rhee ,  Byung-Koan Kim ,  Ock-Chul Shin

    IPC分类号： H03K19/00 ,  H03K19/096

    CPC分类号： H03K19/0963

    摘要： A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

    摘要翻译： 多米诺逻辑电路包括输入电路和输出电路。 输入电路在时钟信号的第一阶段预充电动态节点。 输入电路通过在时钟信号的第二阶段执行输入数据的逻辑评估来确定动态节点的逻辑电平。 输出电路耦合在输出节点和动态节点之间。 输出电路响应于时钟信号和动态节点的逻辑电平来确定输出节点的逻辑电平。 当执行逻辑评估时，输出电路维持输出节点的逻辑电平。

    Timing controller capable of removing surge signal and display apparatus including the same
    5.
    发明授权
    Timing controller capable of removing surge signal and display apparatus including the same 有权
    具有去除浪涌信号的定时控制器和包括其的显示装置

    公开(公告)号：US08711076B2

    公开(公告)日：2014-04-29

    申请号：US12574198

    申请日：2009-10-06

    申请人： Ock Chul Shin ,  Yeong Cheol Rhee ,  Byung Koan Kim

    发明人： Ock Chul Shin ,  Yeong Cheol Rhee ,  Byung Koan Kim

    IPC分类号： G09G3/36

    CPC分类号： G09G5/006

    摘要： A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal.

    摘要翻译： 定时控制器包括：第一级去除在数据使能信号的第一逻辑电平周期期间产生的第一浪涌信号;以及第二级，接收由第一级产生的数据使能信号，并去除在第二逻辑期间产生的第二浪涌信号 接收数据使能信号的电平周期。

    TIMING CONTROLLER CAPABLE OF REMOVING SURGE SIGNAL AND DISPLAY APPARATUS INCLUDING THE SAME
    7.
    发明申请
    TIMING CONTROLLER CAPABLE OF REMOVING SURGE SIGNAL AND DISPLAY APPARATUS INCLUDING THE SAME 有权
    可移除显示信号的定时控制器和包括其的显示设备

    公开(公告)号：US20100085368A1

    公开(公告)日：2010-04-08

    申请号：US12574198

    申请日：2009-10-06

    申请人： Ock Chul SHIN ,  Yeong Cheol Rhee ,  Byung Koan Kim

    发明人： Ock Chul SHIN ,  Yeong Cheol Rhee ,  Byung Koan Kim

    IPC分类号： G06F13/372 ,  G09G3/36

    CPC分类号： G09G5/006

    摘要： A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal.

    摘要翻译： 定时控制器包括：第一级去除在数据使能信号的第一逻辑电平周期期间产生的第一浪涌信号;以及第二级，接收由第一级产生的数据使能信号，并去除在第二逻辑期间产生的第二浪涌信号 接收数据使能信号的电平周期。

    SKEW ADJUSTMENT CIRCUIT AND A METHOD THEREOF
    8.
    发明申请
    SKEW ADJUSTMENT CIRCUIT AND A METHOD THEREOF 有权
    SKEW调整电路及其方法

    公开(公告)号：US20090206897A1

    公开(公告)日：2009-08-20

    申请号：US12247713

    申请日：2008-10-08

    申请人： Byung-koan Kim ,  Ock-chul Shin ,  Young-chul Rhee

    发明人： Byung-koan Kim ,  Ock-chul Shin ,  Young-chul Rhee

    IPC分类号： H03L7/06 ,  H03L7/00

    CPC分类号： H04L25/14 ,  H04L7/0008 ,  H04L7/0037

    摘要： Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.

    摘要翻译： 提供了一种偏斜调整电路及其方法。 偏斜调整电路输入输入时钟信号和输入起始脉冲信号，输出根据偏斜控制信号的偏斜值延迟的输出时钟信号和输出起始脉冲信号。 偏斜调整电路包括延迟电路，选择电路和输出电路。 响应于偏斜控制信号，延迟电路使输入时钟信号延迟偏斜值以产生输出时钟信号。 选择电路比较偏斜控制信号和偏移控制信号，以选择输入起始脉冲信号和延迟起始脉冲信号之一，以输出所选择的信号作为起始脉冲信号。 输出电路响应输出时钟信号，输出起始脉冲信号作为输出起始脉冲信号。