公开(公告)号：US20090230994A1

公开(公告)日：2009-09-17

申请号：US12381360

申请日：2009-03-11

申请人： Young-Chul Rhee ,  Byung-Koan Kim ,  Ock-Chul Shin

发明人： Young-Chul Rhee ,  Byung-Koan Kim ,  Ock-Chul Shin

IPC分类号： H03K19/096 ,  H03K19/00

CPC分类号： H03K19/0963

摘要： A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

摘要翻译： 多米诺逻辑电路包括输入电路和输出电路。 输入电路在时钟信号的第一阶段预充电动态节点。 输入电路通过在时钟信号的第二阶段执行输入数据的逻辑评估来确定动态节点的逻辑电平。 输出电路耦合在输出节点和动态节点之间。 输出电路响应于时钟信号和动态节点的逻辑电平来确定输出节点的逻辑电平。 当执行逻辑评估时，输出电路维持输出节点的逻辑电平。

公开(公告)号：US07282958B2

公开(公告)日：2007-10-16

申请号：US10992077

申请日：2004-11-19

申请人： Young-Chul Rhee

发明人： Young-Chul Rhee

IPC分类号： H03K19/094 ,  H03K17/00

CPC分类号： H03K17/693 ,  H03K17/04106 ,  H03K17/04163

摘要： A MUX circuit may include a plurality of inverter pairs for receiving one of a first input signal and a second input signal to generate a plurality of inverter outputs. The circuit may also include a plurality of switches operatively connected to the plurality of inverter pairs and to a single selection signal for selectively transmitting at least one of the inverter outputs representing one of the first and second input signals as a MUX circuit output signal, based on the selection signal. Generating an output signal from the high-speed MUX circuit may include generating the single selection signal therein and transmitting one of the first and second input signal as a MUX circuit output signal, based on the single selection signal.

摘要翻译： MUX电路可以包括多个逆变器对，用于接收第一输入信号和第二输入信号中的一个以产生多个反相器输出。 电路还可以包括可操作地连接到多个反相器对的多个开关和单个选择信号，用于选择性地将表示第一和第二输入信号之一的逆变器输出中的至少一个作为MUX电路输出信号发送 对选择信号。 从高速MUX电路产生输出信号可以包括在其中产生单个选择信号，并且基于单个选择信号将第一和第二输入信号中的一个作为MUX电路输出信号发送。

公开(公告)号：US20070159239A1

公开(公告)日：2007-07-12

申请号：US11649050

申请日：2007-01-03

申请人： Young-Chul Rhee

发明人： Young-Chul Rhee

IPC分类号： G05F1/10

CPC分类号： H03K17/6872 ,  H03K19/0016 ,  H03K2217/0036

摘要： A power gating structure controls a connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes. The power gating structure includes a first path and a second path. In an active mode, the first path electrically couples the power supply terminal with the virtual power supply node in response to a first control signal. In a data retention mode, the second path electrically couples the power supply terminal with the virtual power supply node in response to the first control signal and a second control signal with a predetermined voltage level difference. In a power-down mode, both the first path and the second path electrically isolate the power supply terminal from the virtual power supply node in response to the first control signal and the second control signal.

摘要翻译： 电源门控结构控制电源端子和虚拟电源节点之间的连接，以便以多种操作模式操作逻辑电路。 电源门控结构包括第一路径和第二路径。 在主动模式中，响应于第一控制信号，第一路径将电源端子与虚拟电源节点电耦合。 在数据保持模式中，第二路径响应于第一控制信号和具有预定电压电平差的第二控制信号将电源端子与虚拟电源节点电耦合。 在掉电模式下，响应于第一控制信号和第二控制信号，第一路径和第二路径都将电源端子与虚拟电源节点电隔离。

公开(公告)号：US20060181310A1

公开(公告)日：2006-08-17

申请号：US11353527

申请日：2006-02-14

申请人： Young-chul Rhee

发明人： Young-chul Rhee

IPC分类号： H03K19/21

CPC分类号： H03K19/215

摘要： An exclusive-OR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-OR circuit may also include a switch configured to couple an output signal of the NAND gate to an output node when an output signal of the NOR gate is “LOW”, and a pull-down circuit configured to pull down the output node when the output signal of the NOR gate is “HIGH”. An exclusive-NOR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-NOR circuit may also include a switch configured to couple an output signal of the NOR gate to an output node when an output signal of the NAND gate is “HIGH”, and a pull-up circuit configured to pull up the output node when the output signal of the NAND gate is “LOW”.

摘要翻译： 异或电路可以包括被配置为接收多个输入信号的NAND门和被配置为接收多个输入信号的NOR门。 异或电路还可以包括被配置为当“或非”门的输出信号为“低”时将“与非”门的输出信号耦合到输出节点的开关;以及下拉电路，其被配置为将输出节点 当NOR门的输出信号为“高”时。 异或非电路可以包括被配置为接收多个输入信号的NAND门和被配置为接收多个输入信号的NOR门。 异或非电路还可以包括开关，其被配置为当NAND门的输出信号为“高”时将或非门的输出信号耦合到输出节点，并且上拉电路被配置为将输出节点 当NAND门的输出信号为“低”时。

公开(公告)号：US20050225361A1

公开(公告)日：2005-10-13

申请号：US11095490

申请日：2005-04-01

申请人： Young-chul Rhee

发明人： Young-chul Rhee

IPC分类号： G06F1/04 ,  G06F1/10 ,  G06F1/32 ,  H03K3/00

CPC分类号： G06F1/32 ,  G06F1/10

摘要： A clock selection circuit and method may operate to generate a clock signal for a digital processing system. In the clock selection circuit, first and second clock control signals may be generated based on a received control signal and/or the inverse of a received clock signal. A first clock signal may be selected when the first clock control signal is activated, and may be output as the selected clock signal. A second clock signal may be selected when the second clock control signal is activated, and may be output as the selected clock signal. The selection operation of the clock selection circuit may reduce the likelihood that a glitch occurs and/or may reduce the amount of power consumed when compared to a conventional clock selection circuit.

摘要翻译： 时钟选择电路和方法可以操作以产生用于数字处理系统的时钟信号。 在时钟选择电路中，可以基于接收到的控制信号和/或所接收的时钟信号的倒数来产生第一和第二时钟控制信号。 当第一时钟控制信号被激活时，可以选择第一时钟信号，并且可以作为选择的时钟信号输出。 当第二时钟控制信号被激活时，可以选择第二时钟信号，并且可以将其输出为选择的时钟信号。 时钟选择电路的选择操作可以降低与常规时钟选择电路相比发生毛刺发生的可能性和/或可以减少消耗的功率量。

公开(公告)号：US20050162192A1

公开(公告)日：2005-07-28

申请号：US10992077

申请日：2004-11-19

申请人： Young-Chul Rhee

发明人： Young-Chul Rhee

IPC分类号： H03K17/041 ,  H03K17/0416 ,  H03K17/693 ,  H03K19/094

CPC分类号： H03K17/693 ,  H03K17/04106 ,  H03K17/04163

摘要： A MUX circuit may include a plurality of inverter pairs for receiving one of a first input signal and a second input signal to generate a plurality of inverter outputs. The circuit may also include a plurality of switches operatively connected to the plurality of inverter pairs and to a single selection signal for selectively transmitting at least one of the inverter outputs representing one of the first and second input signals as a MUX circuit output signal, based on the selection signal. Generating an output signal from the high-speed MUX circuit may include generating the single selection signal therein and transmitting one of the first and second input signal as a MUX circuit output signal, based on the single selection signal.

摘要翻译： MUX电路可以包括多个逆变器对，用于接收第一输入信号和第二输入信号中的一个以产生多个反相器输出。 电路还可以包括可操作地连接到多个反相器对的多个开关和单个选择信号，用于选择性地将表示第一和第二输入信号之一的逆变器输出中的至少一个作为MUX电路输出信号发送 对选择信号。 从高速MUX电路产生输出信号可以包括在其中产生单个选择信号，并且基于单个选择信号将第一和第二输入信号中的一个作为MUX电路输出信号发送。

公开(公告)号：US07605636B2

公开(公告)日：2009-10-20

申请号：US11649050

申请日：2007-01-03

申请人： Young-Chul Rhee

发明人： Young-Chul Rhee

IPC分类号： H03K3/01

CPC分类号： H03K17/6872 ,  H03K19/0016 ,  H03K2217/0036

摘要： A power gating structure controls a connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes. The power gating structure includes a first path and a second path. In an active mode, the first path electrically couples the power supply terminal with the virtual power supply node in response to a first control signal. In a data retention mode, the second path electrically couples the power supply terminal with the virtual power supply node in response to the first control signal and a second control signal with a predetermined voltage level difference. In a power-down mode, both the first path and the second path electrically isolate the power supply terminal from the virtual power supply node in response to the first control signal and the second control signal.

摘要翻译： 电力门控结构控制电源端子和虚拟电源节点之间的连接，以便以多种操作模式操作逻辑电路。 电源门控结构包括第一路径和第二路径。 在主动模式中，响应于第一控制信号，第一路径将电源端子与虚拟电源节点电耦合。 在数据保持模式中，第二路径响应于第一控制信号和具有预定电压电平差的第二控制信号将电源端子与虚拟电源节点电耦合。 在掉电模式下，响应于第一控制信号和第二控制信号，第一路径和第二路径都将电源端子与虚拟电源节点电隔离。

公开(公告)号：US20090206897A1

公开(公告)日：2009-08-20

申请号：US12247713

申请日：2008-10-08

申请人： Byung-koan Kim ,  Ock-chul Shin ,  Young-chul Rhee

发明人： Byung-koan Kim ,  Ock-chul Shin ,  Young-chul Rhee

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H04L25/14 ,  H04L7/0008 ,  H04L7/0037

摘要： Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.

摘要翻译： 提供了一种偏斜调整电路及其方法。 偏斜调整电路输入输入时钟信号和输入起始脉冲信号，输出根据偏斜控制信号的偏斜值延迟的输出时钟信号和输出起始脉冲信号。 偏斜调整电路包括延迟电路，选择电路和输出电路。 响应于偏斜控制信号，延迟电路使输入时钟信号延迟偏斜值以产生输出时钟信号。 选择电路比较偏斜控制信号和偏移控制信号，以选择输入起始脉冲信号和延迟起始脉冲信号之一，以输出所选择的信号作为起始脉冲信号。 输出电路响应输出时钟信号，输出起始脉冲信号作为输出起始脉冲信号。

公开(公告)号：US06717831B2

公开(公告)日：2004-04-06

申请号：US10153391

申请日：2002-05-22

申请人： Young-Chul Rhee ,  Young-Tak Han ,  Kwang-Ju Lee ,  Jung-Ryul Pyo ,  Jong-ho Lee

发明人： Young-Chul Rhee ,  Young-Tak Han ,  Kwang-Ju Lee ,  Jung-Ryul Pyo ,  Jong-ho Lee

IPC分类号： G11C1500

CPC分类号： G11C15/04

摘要： A content addressable memory (CAM) device providing higher integration density, high operation speed and low power consumption. The CAM device comprises a memory cell connected between first and second nodes, first and second data lines for transmitting first and second data signals to the first and second nodes, respectively, and first and second switching devices serially connected between a match line and a reference voltage, wherein the first switching device is controlled by the first data signal and a voltage of the first node and the second switching device is controlled by the second data signal and a voltage of the second node.

摘要翻译： 内容可寻址存储器（CAM）器件提供更高的集成密度，高操作速度和低功耗。 CAM装置包括连接在第一和第二节点之间的存储单元，分别用于将第一和第二数据信号发送到第一和第二节点的第一和第二数据线以及串联连接在匹配线和参考线之间的第一和第二开关装置 电压，其中所述第一开关器件由所述第一数据信号控制，并且所述第一节点和所述第二开关器件的电压由所述第二数据信号和所述第二节点的电压控制。

公开(公告)号：US08139014B2

公开(公告)日：2012-03-20

申请号：US12247713

申请日：2008-10-08

申请人： Byung-koan Kim ,  Ock-chul Shin ,  Young-chul Rhee

发明人： Byung-koan Kim ,  Ock-chul Shin ,  Young-chul Rhee

IPC分类号： G09G3/36

CPC分类号： H04L25/14 ,  H04L7/0008 ,  H04L7/0037

摘要： Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.

摘要翻译： 提供了一种偏斜调整电路及其方法。 偏斜调整电路输入输入时钟信号和输入起始脉冲信号，输出根据偏斜控制信号的偏斜值延迟的输出时钟信号和输出起始脉冲信号。 偏斜调整电路包括延迟电路，选择电路和输出电路。 响应于偏斜控制信号，延迟电路使输入时钟信号延迟偏斜值以产生输出时钟信号。 选择电路比较偏斜控制信号和偏移控制信号，以选择输入起始脉冲信号和延迟起始脉冲信号之一，以输出所选择的信号作为起始脉冲信号。 输出电路响应输出时钟信号，输出起始脉冲信号作为输出起始脉冲信号。