公开(公告)号：US08856426B2

公开(公告)日：2014-10-07

申请号：US13201699

申请日：2010-02-16

Applicant: Mutsuhiro Ohmori

Inventor： Mutsuhiro Ohmori

IPC: G06F12/00 ,  G11C16/22 ,  G11C16/06

CPC classification number: G11C16/06 ,  G11C16/22

Abstract: There is provided a memory device capable of stably storing recorded data over a long term of several decades or longer and capable of reliably reading stored data. A first circuit 200 and a second circuit 300 are separately implementable, and the first circuit 200 includes a data recording circuit 210 reading recorded data from an address appointed by an address signal when a read/write signal stays at a first level and writing data to the address appointed by the address signal when the read/write signal stays at a second level, and a write/read control circuit 230 performing data write/read control on the data recording circuit according to the address signal in response to a read or write instruction from the second circuit.

Abstract translation: 提供了一种能够在几十年或更长时间内长期稳定地存储记录数据并能够可靠地读取存储的数据的存储装置。 第一电路200和第二电路300可单独实现，并且第一电路200包括数据记录电路210，当读/写信号保持在第一电平并且将数据写入到数据记录电路210时，从地址信号指定的地址读取记录数据 当读/写信号保持在第二电平时由地址信号指定的地址;以及写/读控制电路230，响应于读或写，根据地址信号对数据记录电路执行数据写/读控制 来自第二回路的指令。

公开(公告)号：US08539167B2

公开(公告)日：2013-09-17

申请号：US11892722

申请日：2007-08-27

Applicant: Mutsuhiro Ohmori ,  Motofumi Kashiwaya

Inventor： Mutsuhiro Ohmori ,  Motofumi Kashiwaya

IPC: G06F12/00

CPC classification number: G06F13/4022

Abstract: A shared memory device is disclosed which includes: a plurality of processor elements; a plurality of memory modules configured to be accessible by the plurality of processor elements; and a connection device configured to enable a specific processor element out of the plurality of processor elements to access a specific memory module out of the plurality of memory modules; wherein the plurality of processor elements are allowed to access via the connection device a plurality of memory systems each constituted by at least one memory module; and wherein each of the plurality of memory systems accessible by different processor elements allows the plurality of memory modules to be partially shared and accessed by the different processor elements.

Abstract translation: 公开了一种共享存储器件，其包括：多个处理器元件; 多个存储器模块，被配置为可被所述多个处理器元件访问; 以及连接装置，被配置为使得所述多个处理器元件中的特定处理器元件能够访问所述多个存储器模块中的特定存储器模块; 其中所述多个处理器元件被允许经由所述连接装置访问各自由至少一个存储器模块构成的多个存储器系统; 并且其中由不同处理器元件访问的多个存储器系统中的每一个允许所述多个存储器模块被不同的处理器元件部分地共享和访问。

公开(公告)号：US07271488B2

公开(公告)日：2007-09-18

申请号：US11312709

申请日：2005-12-21

Applicant: Tomofumi Arakawa ,  Mutsuhiro Ohmori

Inventor： Tomofumi Arakawa ,  Mutsuhiro Ohmori

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H03K19/17736 ,  H03K19/17796

Abstract: A semiconductor integrated circuit having a plurality of interconnect layers and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer has a plurality of first interconnect groups and second interconnect groups arranged respectively in a row and a column in a matrix. The first and the second interconnect groups are alternately arranged in each row and in each column of the matrix arranged facing each other between two adjacent interconnect layers. The first and second interconnect groups facing each other between the layers have crossing parts where they can be connected through vias.

Abstract translation: 一种半导体集成电路，具有多个互连层和至少一个通孔连接两个相邻互连层的互连，其中每个互连层具有分别以矩阵形式排列的多个第一互连组和第二互连组。 第一和第二互连组交替布置在矩阵中的每一行中并且每个列中彼此相对布置在两个相邻的互连层之间。 在层之间彼此面对的第一和第二互连组具有交叉部分，在那里它们可以通过通孔连接。

公开(公告)号：US20060151883A1

公开(公告)日：2006-07-13

申请号：US11312709

申请日：2005-12-21

Applicant: Tomofumi Arakawa ,  Mutsuhiro Ohmori

Inventor： Tomofumi Arakawa ,  Mutsuhiro Ohmori

IPC: H01L23/52

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H03K19/17736 ,  H03K19/17796

Abstract: A semiconductor integrated circuit having a plurality of interconnect layers and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer has a plurality of first interconnect groups and second interconnect groups arranged respectively in a row and a column in a matrix. The first and the second interconnect groups are alternately arranged in each row and in each column of the matrix arranged facing each other between two adjacent interconnect layers. The first and second interconnect groups facing each other between the layers have crossing parts where they can be connected through vias.

Abstract translation: 一种半导体集成电路，具有多个互连层和至少一个通孔连接两个相邻互连层的互连，其中每个互连层具有分别以矩阵形式排列的多个第一互连组和第二互连组。 第一和第二互连组交替布置在矩阵中的每一行中并且每个列中彼此相对布置在两个相邻的互连层之间。 在层之间彼此面对的第一和第二互连组具有交叉部分，在那里它们可以通过通孔连接。

公开(公告)号：US07047559B2

公开(公告)日：2006-05-16

申请号：US10039894

申请日：2001-11-08

Applicant: Mutsuhiro Ohmori

Inventor： Mutsuhiro Ohmori

IPC: G06F17/30

CPC classification number: G06Q20/04 ,  G06Q20/02 ,  G06Q20/3674 ,  G06Q20/3823 ,  G07B15/02 ,  G07B15/063 ,  G07C9/00111 ,  G07C2011/02 ,  H04L29/06 ,  H04L63/0838 ,  H04L67/02 ,  H04L67/12 ,  H04L67/306

Abstract: A portable terminal stores a first URL which specifies personal information of a user stored in a personal server, and transmits the first URL to a settlement device. The settlement device serves as a network access port for the portable terminal. The personal server is a server which manages personal data of the user that is identified by the first URL, and communicates with the settlement device and a service server via a network. The service server is a server for performing processing identified by a second URL. The service server executes the processing thereof by communicating with the settlement server and personal server via the network. Thus, the user can receive various types of services. Accordingly, a service providing system can be used with a portable terminal that does not hold any personal information therein.

公开(公告)号：US20120185859A1

公开(公告)日：2012-07-19

申请号：US13389134

申请日：2010-08-05

Applicant: Motofumi Kashiwaya ,  Mutsuhiro Ohmori ,  Kurniawan Warih

Inventor： Motofumi Kashiwaya ,  Mutsuhiro Ohmori ,  Kurniawan Warih

IPC: G06F9/46

CPC classification number: G06F9/3832 ,  G06F9/30076 ,  G06F9/3808 ,  G06F9/381

Abstract: History memory 430 correlates the input values and execution result of a function for each piece of function identification information, and holds as an execution history. A command decoder 320 supplies function identification information included in a previous notice command for predicting the function from a fetch unit 310 to an execution history search unit 410. Also, the command decoder 320 causes the execution history search unit 410 to obtain the input value output from an input selecting unit 332 based on, of commands to be read out after the previous notice command, an input value setting command for setting a function input value. The execution history search unit 410 searches an execution history agreeing with the obtained identification information and input values thereof before a function call-up command. An execution result output unit 420 outputs the execution result detected by the execution history search unit 410 to an executing unit 330. The fetch unit 310 reads out a command to be read out following the function.

Abstract translation: 历史存储器430将每个功能识别信息的功能的输入值和执行结果相关联，并保持为执行历史。 命令解码器320将包括在先前通知命令中的功能识别信息提供给执行历史搜索单元410.此外，命令解码器320使得执行历史搜索单元410获得输入值输出 从输入选择单元332基于在先前通知命令之后要读出的命令，输入用于设置功能输入值的输入值设置命令。 执行历史搜索单元410在功能调用命令之前搜索与获得的识别信息一致的执行历史及其输入值。 执行结果输出单元420将由执行历史搜索单元410检测到的执行结果输出到执行单元330.读取单元310读出在该功能之后要读出的命令。

公开(公告)号：US20090150651A1

公开(公告)日：2009-06-11

申请号：US12292310

申请日：2008-11-17

Applicant: Mutsuhiro Ohmori

Inventor： Mutsuhiro Ohmori

IPC: G06F1/26 ,  G06F9/00

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: Disclosed herein is a semiconductor chip including: a plurality of processing devices that can communicate with each other; wherein each of the processing devices includes an arithmetic unit, an individual memory connected to the arithmetic unit on a one-to-one basis, and a control unit configured to independently control turning on and off of operation of the arithmetic unit and the individual memory.

Abstract translation: 这里公开了一种半导体芯片，包括：能够彼此通信的多个处理装置; 其中每个所述处理装置包括运算单元，一对一连接到所述运算单元的单独存储器，以及控制单元，被配置为独立地控制所述运算单元和所述单独存储器的运行的导通和关断 。

公开(公告)号：US07411412B2

公开(公告)日：2008-08-12

申请号：US11499730

申请日：2006-08-07

Applicant: Tomofumi Arakawa ,  Mutsuhiro Ohmori

Inventor： Tomofumi Arakawa ,  Mutsuhiro Ohmori

IPC: H03K19/003 ,  G06F7/38

CPC classification number: H03K19/00392

Abstract: A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.

Abstract translation: 一种半导体集成电路，包括：根据输入功能设置数据设置其功能的N个模块，具有R个I / O部分的电路块，以及用于从N个模块中选择R个模块的模块选择部分 连接所选择的R个模块和R个电路块的I / O部分，并将从至少两个模块中选出的一个模块连接到R个I / O部分中的每一个。 R个I / O部分中的每一个具有用于保持功能设置数据并将保持的功能设置数据输入到目的地模块的数据保持部分，并且当输入功能设置数据时，N个模块能够替换彼此的功能 是相同的。

公开(公告)号：US20070057690A1

公开(公告)日：2007-03-15

申请号：US11499730

申请日：2006-08-07

Applicant: Tomofumi Arakawa ,  Mutsuhiro Ohmori

Inventor： Tomofumi Arakawa ,  Mutsuhiro Ohmori

IPC: H03K19/003

CPC classification number: H03K19/00392

Abstract: A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.

Abstract translation: 一种半导体集成电路，包括：根据输入功能设置数据设置其功能的N个模块，具有R个I / O部分的电路块，以及用于从N个模块中选择R个模块的模块选择部分 连接所选择的R个模块和R个电路块的I / O部分，并将从至少两个模块中选出的一个模块连接到R个I / O部分中的每一个。 R个I / O部分中的每一个具有用于保持功能设置数据并将保持的功能设置数据输入到目的地模块的数据保持部分，并且当输入功能设置数据时，N个模块能够替换彼此的功能 是相同的。

公开(公告)号：US07583270B2

公开(公告)日：2009-09-01

申请号：US09789597

申请日：2001-02-22

Applicant: Mutsuhiro Ohmori ,  Toshio Horioka

Inventor： Mutsuhiro Ohmori ,  Toshio Horioka

IPC: G06F12/00

CPC classification number: G06T15/005

Abstract: An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.