公开(公告)号：US20060194564A1

公开(公告)日：2006-08-31

申请号：US10565835

申请日：2004-07-29

申请人： Takehiro Hokimoto ,  Daisuke Kawasaki ,  Masanobu Arai ,  Kaname Kojima

发明人： Takehiro Hokimoto ,  Daisuke Kawasaki ,  Masanobu Arai ,  Kaname Kojima

IPC分类号： H04B1/16 ,  H04B1/38

CPC分类号： H04W52/0235 ,  H04W88/02 ,  Y02D70/00

摘要： A radio transmitter/receiver and an intermittent transmission/reception control method thereof, capable of reducing the reception startup time as well as suppressing reception power consumption. A radio transmitter/receiver used for ad hoc communication is provided with a dedicated standby reception unit (10) having a simple combination of an RF demodulator (6) and a SAW oscillator (7) only to detect a carrier. For a time period of several bits, the activation system of the radio transmitter/receiver intermittently receives activation selection signals transmitted using ASK (or OOK) modulation prior to a preamble signal, and makes an activation selection based on the pattern of presence and absence of the carriers of the signals. As a result, the reception startup time can be shortened, and less reception power is required.

摘要翻译： 一种无线电发射机/接收机及其间歇发送/接收控制方法，其能够减少接收启动时间以及抑制接收功率消耗。 用于自组织通信的无线电发射机/接收机设置有仅具有RF解调器（6）和SAW振荡器（7）的简单组合的仅用于检测载波的专用待机接收单元（10）。 在几比特的时间段内，无线电发射机/接收机的激活系统间歇地接收在前导信号之前使用ASK（或OOK）调制发射的激活选择信号，并且基于存在和不存在的模式进行激活选择 信号的载体。 结果，可以缩短接收启动时间，并且需要较少的接收功率。

公开(公告)号：US20050163088A1

公开(公告)日：2005-07-28

申请号：US11043172

申请日：2005-01-27

申请人： Satoru Yamano ,  Masanobu Arai

发明人： Satoru Yamano ,  Masanobu Arai

IPC分类号： H04L12/28 ,  H04B7/155 ,  H04B7/26 ,  H04W16/26 ,  H04W28/18 ,  H04W52/02 ,  H04W74/04 ,  H04W74/08 ,  H04W84/12 ,  H04W88/04 ,  H04Q7/24

CPC分类号： H04W28/18 ,  H04W52/0219 ,  H04W52/0261 ,  H04W88/04 ,  Y02D70/20

摘要： A radio communication method, a radio communication system and a wireless terminal by which low power consumption and the flexibility of a network can be realized. A base station and wireless terminals change an intermittent receive period and the preamble length of data on the basis of characteristics of the multihop radio network to carry out the intermittent receiving of data. Thus, a wireless terminal relaying data can receive the data reliably and a useless boot-up of a receiving part and standby time can be largely reduced to achieve low power consumption.

摘要翻译： 无线电通信方法，无线电通信系统和无线终端，能够实现低功耗和网络的灵活性。 基站和无线终端基于多跳无线电网络的特性改变间歇接收周期和数据的前导码长度，以执行数据的间歇接收。 因此，无线终端中继数据可以可靠地接收数据，并且可以大大减少接收部分的无用启动和待机时间以实现低功耗。

公开(公告)号：US5490182A

公开(公告)日：1996-02-06

申请号：US248254

申请日：1994-05-24

申请人： Masanobu Arai

发明人： Masanobu Arai

IPC分类号： H03L7/06 ,  H03K3/03 ,  H03L7/099 ,  H03D3/24

CPC分类号： H03L7/0997 ,  H03K3/0315

摘要： A phase-locked loop circuit has a ring oscillator comprising a plurality of 1st, 2nd, . . . , nth inverter chains composed of series-connected 21, 22, . . . , 2n inverters (n.gtoreq.2), respectively, an (n+1)th inverter chain composed of an odd number of series-connected inverters, and a plurality of 1st-nth selectors associated with the 1st-nth inverter chains, respectively, for selectively outputting input signals to and output signals from the 1st-nth inverter chains, the 1st-nth inverter chains being combined respectively with the 1st-nth selectors in respective combinations, the combinations and the (n+1)th inverter chain being connected in a ring configuration. A phase comparator compares an input clock signal and an oscillated clock signal from the ring oscillator in phase, and applies an output signal to a control circuit which controls the 1st-nth selectors to synchronize the oscillated clock signal with the input clock signal.

摘要翻译： 锁相环电路具有环形振荡器，该环形振荡器包括多个第一，第二，第二。 。 。 ，第n个逆变器链由串联21,22组成。 。 。 ，2n个变换器（n> / = 2），分别由奇数个串联逆变器构成的第（n + 1）个反相器链和与第1〜第n反相器链相关联的多个第1〜第n选择器， 分别用于选择性地输出输入信号并输出​​来自第1〜第n反相器链的信号，第1〜第n反相器链分别与第1〜第n选择器组合，组合和第（n + 1）个反相器链 以环形配置连接。 相位比较器将输入时钟信号和来自环形振荡器的振荡时钟信号进行相位比较，并将输出信号施加到控制电路，控制电路使第1〜第n选择器与振荡时钟信号与输入时钟信号同步。

公开(公告)号：US5189378A

公开(公告)日：1993-02-23

申请号：US756067

申请日：1991-09-06

申请人： Masanobu Arai

发明人： Masanobu Arai

IPC分类号： H03K5/19 ,  H04L7/033

CPC分类号： H03K5/19 ,  H04L7/0334

摘要： A tone signal detecting circuit includes a sampling circuit, a storage circuit, and a comparing circuit. The sampling circuit samples a tone signal at a sampling rate N times (N is a natural number) higher than a frequency f of the one signal. The storage circuit stores M (M is a natural number) latest values of time series data from the sampling circuit. The comparing circuit compares a plurality of polarity patterns expected on the basis of a tone signal with polarity patterns stored in the storage circuit and outputting coincidence outputs.

摘要翻译： 音调信号检测电路包括采样电路，存储电路和比较电路。 采样电路以比该一个信号的频率f高N倍（N是自然数）的采样率对音调信号进行采样。 存储电路存储来自采样电路的时间序列数据的M（M是自然数）最新值。 比较电路将基于音调信号预期的多个极性图案与存储在存储电路中的极性图案进行比较，并输出一致输出。

公开(公告)号：US5048060A

公开(公告)日：1991-09-10

申请号：US271979

申请日：1988-11-16

申请人： Masanobu Arai ,  Masaru Yamaguchi ,  Takenori Ogata

发明人： Masanobu Arai ,  Masaru Yamaguchi ,  Takenori Ogata

IPC分类号： H04L7/02 ,  H04L7/033

CPC分类号： H04L7/0054 ,  H04L7/0334

摘要： In a baude rate sampling type receiving circuit for use in a system for transmitting digital data signal at a transmission baude rate, in order to control the sampling phase at the optimum phase, desired elements of an autocorrelation function of a series of baud rate sampled signals are calculated and are linearly summed by a calculating circuit to provide a linear summation as a power of the series of sampled signals. The sampling phase at the baud rate sampling is controlled by a control circuit by use of the linear summation so that the power is maximized, whereby the sampling phase is maintained at the optimum sampling phase.

公开(公告)号：US4888762A

公开(公告)日：1989-12-19

申请号：US156711

申请日：1988-02-17

申请人： Masanobu Arai

发明人： Masanobu Arai

IPC分类号： H04B3/23

CPC分类号： H04B3/23 ,  H04B3/238

摘要： An echo canceller for bidirectional transmission on two-wire metallic subscriber lines in an integrated service digital network employing a filter positioned in the echo path having the property that a zero point is located so as to cancel the echo path transfer function attributable to the inductance component of the line coupling transformer.

摘要翻译： 一种用于在综合业务数字网络中的双线金属用户线路上进行双向传输的回波消除器，其使用位于回波路径中的具有零点位置的属性的滤波器，以消除归因于电感分量的回波路径传递函数 的线耦合变压器。

公开(公告)号：US5885229A

公开(公告)日：1999-03-23

申请号：US684676

申请日：1996-07-19

申请人： Junji Yamato ,  Kyoko Sudo ,  Akira Tomono ,  Masanobu Arai

发明人： Junji Yamato ,  Kyoko Sudo ,  Akira Tomono ,  Masanobu Arai

IPC分类号： A61B5/103

CPC分类号： A61B5/1038 ,  A61B5/742

摘要： According to the present invention, two-dimensional pressure distribution associated with walking are collected at a preselected time interval as time series pressure distribution images, superposed images are formed by superposing the time series pressure distribution images in a time direction, a plurality of foot pressure mass regions are extracted from the superposed images, correspondence of each foot pressure mass region to the time series pressure distribution images are detected, feature parameters associated with the walking are detected based on the correspondence, and the feature parameters are displayed or printed.

摘要翻译： 根据本发明，与步行相关联的二维压力分布以预选的时间间隔收集为时间序列压力分布图像，叠加图像通过在时间方向上叠加时间序列压力分布图像，多个脚压 从叠加图像中提取质量区域，检测每个脚压力质量区域与时间序列压力分布图像的对应关系，基于对应性检测与行走相关联的特征参数，并且显示或打印特征参数。

公开(公告)号：US5406145A

公开(公告)日：1995-04-11

申请号：US160812

申请日：1993-12-03

申请人： Masanobu Arai ,  Noriaki Edasawa

发明人： Masanobu Arai ,  Noriaki Edasawa

IPC分类号： H03F1/30 ,  H03F3/30 ,  G06G7/10

CPC分类号： H03F1/308 ,  H03F3/3001

摘要： A push-pull-type amplifier circuit has three current mirror circuits CM1, CM2, CM3 and transistors M6, M7 connected between a reference current supply I.sub.R and output transistors M2, M3 for controlling an idling current flowing through the output transistors M2, M3 so as to be proportional to a current flowing through the reference current supply I.sub.R so that the idling current will be stabilized irrespective of variations in a power supply voltage. An operational amplifier which incorporates the push-pull-type amplifier circuit as an output stage circuit is highly stable in operation, and can be designed in a simple arrangement without having to take into account power supply voltage variations.

摘要翻译： 推挽型放大器电路具有连接在参考电流源IR和输出晶体管M2，M3之间的三个电流镜电路CM1，CM2，CM3和晶体管M6，M7，用于控制流过输出晶体管M2，M3的空转电流，以便 与流过参考电流源IR的电流成比例，使得怠速电流将稳定，而与电源电压的变化无关。 将推挽式放大器电路作为输出级电路并入的运算放大器在操作中高度稳定，并且可以以简单的布置设计，而不必考虑电源电压变化。

公开(公告)号：US5103185A

公开(公告)日：1992-04-07

申请号：US583289

申请日：1990-09-17

申请人： Masanobu Arai

发明人： Masanobu Arai

IPC分类号： H04L7/02 ,  H03K5/135 ,  H03K5/156 ,  H04L7/00 ,  H04L7/033 ,  H04L7/04

CPC分类号： H04L7/0338 ,  H03K5/135 ,  H03K5/1565 ,  H04L7/0083 ,  H04L7/044

摘要： A clock jitter suppressing circuit includes a control circuit, a delay circuit, and a selection circuit. The delay circuit sequentially delays a clock signal at time intervals sufficiently shorter than the period of the clock signal. The selection circuit selects and outputs one of delay outputs from the delay circuit which is determined in accordance with a selection signal. The control circuit generates a selection signal for selecting a predetermined delay output when no jitter is caused in the clock signal. Every time jitter is caused in the clock signal, the control circuit generates a selection signal for selecting a delay output which is shifted by an amount corresponding to the phase amount of the jitter in a direction to cancel a polarity of the jitter.

公开(公告)号：US5042026A

公开(公告)日：1991-08-20

申请号：US161808

申请日：1988-02-29

申请人： Shin'ichi Koike ,  Masaru Yamaguchi ,  Masanobu Arai ,  Takenori Ogata

发明人： Shin'ichi Koike ,  Masaru Yamaguchi ,  Masanobu Arai ,  Takenori Ogata

IPC分类号： H03H17/02 ,  H04B3/23

CPC分类号： H04B3/235 ,  H03H17/0288 ,  H04B3/238

摘要： The whole or part of a waveform is cancelled by a circuit comprising a nonrecursive filter and a recursive filter. The nonrecursive filter has a plurality of first multipliers having first tap weights for modifying symbols successively shifted along a shift register. The recursive filter is connected in a series circuit to the shift register and has a second tap weight for recursively modifying the output of the shift register. The recursively modified symbol is modified by a second multiplier having a third tap weight and combined in an adder with the symbols modified by the first tap weights to produce a replica of an undesired waveform. The replica is destructively combined in a subtractor with an incoming symbol having an undesired waveform. The output of subtractor is utilized to derive the tap weights to adaptively control the inputs to the adder.