知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.014 秒)

    INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES
    2.
    发明申请
    INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES 有权
    中断处理员队伍的中断设施

    公开(公告)号：US20100100656A1

    公开(公告)日：2010-04-22

    申请号：US12254892

    申请日：2008-10-21

    申请人： Charles W. Gainey, JR. ,  Klaus Meissner ,  Damian L. Osisek ,  Klaus Werner

    发明人： Charles W. Gainey, JR. ,  Klaus Meissner ,  Damian L. Osisek ,  Klaus Werner

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

    摘要翻译： 辅助处理器队列的中断设施。 响应于队列从无应答等待状态转移到回复挂起状态，发起中断。 该中断向处理器通知对请求的响应在队列上等待。 为了使队列利用中断能力，它可以被中断。

    Calibration standard for profilometers and manufacturing procedure
    4.
    发明授权
    Calibration standard for profilometers and manufacturing procedure 失效
    轮廓仪和制造程序的校准标准

    公开(公告)号：US6028008A

    公开(公告)日：2000-02-22

    申请号：US987213

    申请日：1997-12-09

    申请人： Thomas Bayer ,  Johann Greschner ,  Klaus Meissner

    发明人： Thomas Bayer ,  Johann Greschner ,  Klaus Meissner

    IPC分类号： G01B5/02 ,  G01B5/18 ,  H01L21/00

    CPC分类号： G01Q40/02 ,  B82Y35/00 ,  G01B5/02 ,  G01B5/18

    摘要： The invention relates to calibration standards which are used chiefly for the calibration of profilometers and in atomic force- and scanning probe microscopes. The calibration standard has one step of defined height H or a multi-step system formed of several steps of the same step-height H and consisting of exactly one material. The manufacturing procedure for the calibration standard requires only a single masking layer for each of the different versions in the form of a one-step standard or a multi-step system.

    摘要翻译： 本发明涉及主要用于校准轮廓仪和原子力扫描探针显微镜的校准标准。 校准标准具有定义的高度H或由相同步长H的几个步骤形成的多个步骤系统的一个步骤，并且由恰好一个材料组成。 校准标准的制造程序只需要一个单步骤标准或多步骤系统形式的不同版本的每个单一屏蔽层。

    Membrane mask for electron beam lithography
    5.
    发明授权
    Membrane mask for electron beam lithography 失效
    电子束光刻膜罩

    公开(公告)号：US6004700A

    公开(公告)日：1999-12-21

    申请号：US40099

    申请日：1998-03-17

    申请人： Johann Greschner ,  Samuel Kalt ,  Klaus Meissner ,  Rudolf Paul

    发明人： Johann Greschner ,  Samuel Kalt ,  Klaus Meissner ,  Rudolf Paul

    IPC分类号： G03F1/20 ,  H01L21/027 ,  G03F9/00

    CPC分类号： G03F1/20

    摘要： Membrane masks for electron-beam lithography are described which have a high mechanical stability and low membrane thickness, are free of stress and the submicron structures of which are easy to produce using reactive ion etching methods without rounding effects.In the case of a membrane mask for structuring surface areas with the aid of electron or corpuscular beams, a layer 1 of silicon nitride with going right through openings, which define the mask pattern, is deposited on one surface of a semiconductor wafer 2, which consists preferably of silicon. A tub-shaped recess 3 extends from the other surface of the semiconductor wafer 2 as far as the layer-carrying surface.A further mask for structuring surface areas with the aid of electron beams has at least one continuous layer 30 and a layer 31 defining the mask pattern.These two layers are deposited on the surface of a semiconductor wafer 32 with a tub-shaped recess 33.The anisotropic plasma etching method according to the invention makes it possible to transfer lithographically produced patterns to the membrane without the edge rounding which is otherwise usual.

    摘要翻译： 描述了用于电子束光刻的膜掩模，其具有高机械稳定性和低膜厚度，没有应力，并且其亚微米结构易于使用没有圆整效应的反应离子蚀刻方法产生。 在用于借助于电子或微粒束结构化表面区域的膜掩模的情况下，在半导体晶片2的一个表面上沉积限定掩模图案的直通通孔的氮化硅层1， 优选由硅组成。 桶形凹部3从半导体晶片2的另一个表面延伸到层承载表面。 借助于电子束来构造表面区域的另一个掩模具有至少一个连续层30和限定掩模图案的层31。 这两层沉积在具有桶状凹部33的半导体晶片32的表面上。根据本发明的各向异性等离子体蚀刻方法使得可以将光刻产生的图案转印到膜上而不进行通常的边缘倒圆。

    Process for the creation of a thermal SiO.sub.2 layer with extremely uniform layer thickness
    6.
    发明授权
    Process for the creation of a thermal SiO.sub.2 layer with extremely uniform layer thickness 失效
    用于产生具有非常均匀层厚度的热SiO 2层的工艺

    公开(公告)号：US5817581A

    公开(公告)日：1998-10-06

    申请号：US702608

    申请日：1996-08-26

    申请人： Thomas Bayer ,  Johann Greschner ,  Klaus Meissner

    发明人： Thomas Bayer ,  Johann Greschner ,  Klaus Meissner

    IPC分类号： H01L21/316

    CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662

    摘要： Disclosed is a reproducible process for making an SiO.sub.2 layer by thermal oxidation which assures an extremely uniform thickness of the SiO.sub.2 layer of approximately 1%. The process of the invention comprises the steps growing an initial layer of SiO.sub.2 to a defined minimal thickness by dry oxidation and increasing the thickness of the initial layer by simultaneous wet and dry oxidation until the desired final thickness is reached.

    摘要翻译： PCT No.PCT / EP95 / 01518 Sec。 371日期：1996年8月26日 102（e）日期1996年8月26日PCT提交1995年4月21日PCT公布。 第WO96 / 33510号公报 日期1996年10月24日公开是通过热氧化制备SiO 2层的可再现方法，其确保SiO 2层的非常均匀的厚度约为1％。 本发明的方法包括通过干式氧化将SiO 2的初始层增长到限定的最小厚度的步骤，并通过同时湿式和干式氧化增加初始层的厚度，直到达到所需的最终厚度。

    Process for making masks with structures in the submicron range
    7.
    发明授权
    Process for making masks with structures in the submicron range 失效
    用于制作带有结构的遮罩的方法

    公开(公告)号：US5055383A

    公开(公告)日：1991-10-08

    申请号：US420870

    申请日：1989-10-12

    申请人： Otto Koblinger ,  Klaus Meissner ,  Reinhold Muhl ,  Hans-Joachim Trumpp ,  Werner Zapka

    发明人： Otto Koblinger ,  Klaus Meissner ,  Reinhold Muhl ,  Hans-Joachim Trumpp ,  Werner Zapka

    IPC分类号： G03F1/08 ,  G03F7/00 ,  G03F7/09 ,  H01L21/027 ,  H01L21/30 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

    CPC分类号： G03F7/0035 ,  G03F7/094 ,  H01L21/0271 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31144

    摘要： In the course of the process for making masks with structures in the submicrometer range, initially structures of photoresist or polymer material with horizontal and substantially vertical sidewalls are produced on a silicon substrate covered with an oxide layer. This is followed by a layer of silicon nitride which is deposited by LPCVD. The resultant structure is planarized with a photoresist which is etched back until the start of the vertical edges of the sidewall coating formed by the nitride layer is bared on the photoresist structures. In a photolithographic step, a trimming mask is produced on the surface of the nitride layer and the planarizing resist. The bared regions of the nitride layer are then removed by isotropic etching. The dimensions A-B of the openings defined after removal of the nitride layer from the vertical surfaces of the photoresist structures are transferred to the oxide layer by anisotropic etching. Concurrently with these structures of minimum line width, registration marks are generated which allow the adjustment necessary for a further photolithographic step to be carried out with maximum accuracy. After removal of the trimming mask, the planarizing resist, the photoresist structures and the remainder of the nitride layer, structures with coarser line widths are defined in a further photolithographic step, which are also transferred to the oxide layer. Using the oxide layer as a mask, trenches of the desired depth are produced in the silicon substrate by anisotropic etching. The mask is thinned by anisotropic etching, and the oxide layers are removed from the front and the back side by wet etching.

    摘要翻译： 在制造具有亚微米范围内的结构的掩模的过程中，最初在被氧化物层覆盖的硅衬底上产生具有水平和基本垂直侧壁的光致抗蚀剂或聚合物材料的结构。 之后是通过LPCVD沉积的一层氮化硅。 所得到的结构被蚀刻后的光致抗蚀剂平坦化，直到由氮化物层形成的侧壁涂层的垂直边缘的开始在光致抗蚀剂结构上露出。 在光刻步骤中，在氮化物层和平坦化抗蚀剂的表面上制造修整掩模。 然后通过各向同性蚀刻除去氮化物层的裸露区域。 在从光致抗蚀剂结构的垂直表面去除氮化物层之后限定的开口的尺寸A-B通过各向异性蚀刻转移到氧化物层。 与最小线宽度的这些结构同时产生对准标记，其允许以最大精度执行进一步的光刻步骤所必需的调整。 在去除修剪掩模之后，在另外的光刻步骤中限定平坦化抗蚀剂，光致抗蚀剂结构和氮化物层的其余部分，具有较宽线宽的结构也被转移到氧化物层。 使用氧化物层作为掩模，通过各向异性蚀刻在硅衬底中产生所需深度的沟槽。 通过各向异性蚀刻使掩模变薄，并且通过湿蚀刻从前侧和后侧去除氧化物层。

    Apparatus and computer program product for TOD-clock steering
    9.
    发明授权
    Apparatus and computer program product for TOD-clock steering 有权
    用于TOD时钟转向的装置和计算机程序产品

    公开(公告)号：US07681064B2

    公开(公告)日：2010-03-16

    申请号：US11968733

    申请日：2008-01-03

    申请人： Eberhard Engler ,  Mark S. Farrell ,  Klaus Meissner ,  Ronald M. Smith, Sr.

    发明人： Eberhard Engler ,  Mark S. Farrell ,  Klaus Meissner ,  Ronald M. Smith, Sr.

    IPC分类号： G06F1/04 ,  G04C11/00

    CPC分类号： G06F1/14

    摘要： A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes computing a TOD-clock offset value (d) to be added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.

    摘要翻译： 一种用于转向具有物理时钟的计算机系统的时钟（TOD）时钟的系统，方法和计算机程序产品，该物理时钟提供用于执行步进到公共振荡器的操作的时基。 该方法包括计算要添加到物理时钟值（Tr）值的TOD时钟偏移值（d）以获得逻辑TOD时钟值（Tb），其中逻辑TOD时钟值可调整而不调整 振荡器的步进率。

    MANAGING DATA ACCESS VIA A LOOP ONLY IF CHANGED LOCKING FACILITY
    10.
    发明申请
    MANAGING DATA ACCESS VIA A LOOP ONLY IF CHANGED LOCKING FACILITY 有权
    如果更改锁定设施，只能通过环路管理数据访问

    公开(公告)号：US20080059808A1

    公开(公告)日：2008-03-06

    申请号：US11468501

    申请日：2006-08-30

    申请人： Eberhard Engler ,  Klaus Meissner ,  Ronald M. Smith

    发明人： Eberhard Engler ,  Klaus Meissner ,  Ronald M. Smith

    IPC分类号： G06F12/14

    CPC分类号： G06F9/526 ,  G06F9/524 ,  G06F2209/521

    摘要： The management of data access is facilitated. A loop only if changed locking facility is provided, in which reads and updates of the data being managed are permitted, unless an update to the data completes during the execution of the read or update routine. As long as an update to the data has not completed during a processor's execution of the read or update routine, access is permitted.

    摘要翻译： 数据访问管理方便。 只有在提供了改变的锁定设备时，才允许循环，除非在执行读取或更新程序期间对数据的更新完成。 只要数据的更新在处理器执行读取或更新程序期间尚未完成，则允许访问。