公开(公告)号：US08331519B2

公开(公告)日：2012-12-11

申请号：US12430691

申请日：2009-04-27

Applicant: Sergey Zhidkov ,  Jun Ho Huh ,  Ki Seop Kwon

Inventor： Sergey Zhidkov ,  Jun Ho Huh ,  Ki Seop Kwon

IPC: H04L7/00

CPC classification number: G01R23/15 ,  G01R23/10 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0998 ,  H04L7/0334 ,  H04L7/10

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract translation: 频率检测器包括测量被调制的输入信号的过零点之间的时间间隔的误差测量单元。 误差转换单元使用调制时间间隔之一量化测量的时间间隔。 误差计算单元基于测量的时间间隔和量化时间间隔之间的差来计算频率误差。 误差产生控制单元基于量化时​​间间隔，计算出的频率误差和预定临界值来控制是否输出频率误差。

公开(公告)号：US06876584B2

公开(公告)日：2005-04-05

申请号：US10623289

申请日：2003-07-18

Applicant: Ki-Seop Kwon

Inventor： Ki-Seop Kwon

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/34

CPC classification number: G11C7/06 ,  G11C7/12 ,  G11C2207/005 ,  G11C2207/065

Abstract: The present invention provides a semiconductor memory device for reducing operation noise, as a sense amplifier in accordance with the present invention senses and amplifies a supplied data signal of a bit line pair on high speed. For this object, the semiconductor memory device includes a first cell array including a plurality of unit cells to be selected by an address signal; a sense amplifying unit for sensing and amplifying voltage level of a bit line connected to the plurality of the unit cells; a switching unit for connecting or disconnecting the sense amplifying unit to the bit line; and a sense amplifying connection unit for controlling the switching unit for connecting or disconnecting the sense amplifying unit to the first cell array by increasing or decreasing an amount of current throughout the switching unit in response to the address signal.

Abstract translation: 本发明提供一种用于降低操作噪声的半导体存储器件，因为根据本发明的读出放大器以高速度感测和放大位线对的提供的数据信号。 为此目的，半导体存储器件包括：第一单元阵列，其包括由地址信号选择的多个单位单元; 感测放大单元，用于感测和放大连接到所述多个单位单元的位线的电压电平; 用于将读出放大单元连接或断开到位线的切换单元; 以及感测放大连接单元，用于通过响应于地址信号增加或减少整个开关单元中的电流量来控制用于将感测放大单元连接或断开到第一单元阵列的开关单元。

公开(公告)号：US20090310730A1

公开(公告)日：2009-12-17

申请号：US12430691

申请日：2009-04-27

Applicant: Sergey Zhidkov ,  Jun Ho Huh ,  Ki Seop Kwon

Inventor： Sergey Zhidkov ,  Jun Ho Huh ,  Ki Seop Kwon

IPC: H04L7/00 ,  G01R23/02 ,  H03K9/06 ,  H03L7/06 ,  H03L7/00 ,  G01R31/26 ,  G01R23/00

CPC classification number: G01R23/15 ,  G01R23/10 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0998 ,  H04L7/0334 ,  H04L7/10

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract translation: 频率检测器包括测量被调制的输入信号的过零点之间的时间间隔的误差测量单元。 误差转换单元使用调制时间间隔之一量化测量的时间间隔。 误差计算单元基于测量的时间间隔和量化时间间隔之间的差来计算频率误差。 误差产生控制单元基于量化时​​间间隔，计算出的频率误差和预定临界值来控制是否输出频率误差。

公开(公告)号：US06925020B2

公开(公告)日：2005-08-02

申请号：US10737844

申请日：2003-12-18

Applicant: Ki Seop Kwon

Inventor： Ki Seop Kwon

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/08

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C2207/065

Abstract: A semiconductor memory device comprises a plurality of memory cell arrays, a plurality of sense amplifiers, a connection unit, a driver and an over-driver. The plurality of memory cell arrays comprise a plurality of memory cells. The plurality of sense amplifiers sense and amplify data stored in the plurality of memory cells. The connection unit selectively connects the plurality of sense amplifiers to the plurality of memory cell arrays. The driver drives the sense amplifier to a predetermined voltage. The over-driver applies an overdrive voltage to the driver for a predetermined time after the sense amplifier is temporarily separated from the selected memory cell array. In the semiconductor device since data in a bitline can be rapidly amplified, the restoration time of data stored in a memory cell is reduced, and the parameter tRCD. Accordingly, the operation speed of the semiconductor memory device can be improved.

Abstract translation: 半导体存储器件包括多个存储单元阵列，多个读出放大器，连接单元，驱动器和过驱动器。 多个存储单元阵列包括多个存储单元。 多个读出放大器感测并放大存储在多个存储单元中的数据。 连接单元选择性地将多个读出放大器连接到多个存储单元阵列。 驱动器将读出放大器驱动到预定电压。 在感测放大器暂时与选定的存储单元阵列分离之后，过驱动器在驱动器上施加过驱动电压达预定时间。 在半导体器件中，由于可以快速放大位线中的数据，所以存储在存储单元中的数据的恢复时间减少，并且参数tRCD。 因此，可以提高半导体存储器件的操作速度。

公开(公告)号：US06914798B2

公开(公告)日：2005-07-05

申请号：US10865860

申请日：2004-06-14

Applicant: Ki-Seop Kwon ,  Seong-Hoon Lee

Inventor： Ki-Seop Kwon ,  Seong-Hoon Lee

IPC: G06F1/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081 ,  G11C11/22

CPC classification number: H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  H03K5/131 ,  H03K2005/00058 ,  H03K2005/00104 ,  H03L7/0802 ,  H03L7/0814

Abstract: A register controlled delay locked loop (DLL) usable in a semiconductor device is provided. The register controlled delay locked loop includes an internal clock generating unit generating a delayed clock signal and a reference clock signal, a first delay unit compensating for an amount of delay caused by a signal transmission path of the delayed clock signal, a phase comparator detecting a difference between the reference clock signal and the delayed clock signal and thereby generating a detection signal, a controller having a plurality of second delay units for controlling an amount of delay of the delayed clock signal in response to the detection signal, a driver driving a DLL clock signal, and an enable signal generator enabling the driver in response to an activation or non-activation signal of the semiconductor device.

Abstract translation: 提供可用于半导体器件的寄存器控制延迟锁定环（DLL）。 寄存器控制延迟锁定环路包括产生延迟时钟信号和参考时钟信号的内部时钟产生单元，补偿由延迟时钟信号的信号传输路径引起的延迟量的第一延迟单元，相位比较器检测 参考时钟信号和延迟的时钟信号之间的差异，从而产生检测信号;控制器，具有多个第二延迟单元，用于响应于检测信号来控制延迟时钟信号的延迟量;驱动器驱动DLL 时钟信号，以及允许驱动器响应于半导体器件的激活或非激活信号的使能信号发生器。

公开(公告)号：US06768690B2

公开(公告)日：2004-07-27

申请号：US10183666

申请日：2002-06-28

Applicant: Ki-Seop Kwon ,  Seong-Hoon Lee

Inventor： Ki-Seop Kwon ,  Seong-Hoon Lee

IPC: G11C700

CPC classification number: H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  H03K5/131 ,  H03K2005/00058 ,  H03K2005/00104 ,  H03L7/0802 ,  H03L7/0814

Abstract: A resister controlled delay locked loop (DLL) is provided which is capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode. A semiconductor device having the register controlled DLL and an internal circuit synchronized with a DLL clock signal output from the register controlled DLL, includes an enable signal generator generating an enable signal for the register controlled DLL to control a generation of the DLL clock signal in response to an activation or non-activation signal of the semiconductor device.

Abstract translation: 提供电阻控制延迟锁定环（DLL），其能够在半导体器件仅处于操作模式时通过操作DLL环路来减少电流消耗。 具有寄存器控制DLL和与从寄存器控制的DLL输出的DLL时钟信号同步的内部电路的半导体器件包括使能信号发生器产生用于寄存器控制的DLL的使能信号，以响应于控制DLL时钟信号的产生 涉及半导体器件的激活或非激活信号。