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    Transceiver with latency alignment circuitry
    1.
    发明授权
    Transceiver with latency alignment circuitry 有权
    具有延迟对准电路的收发器

    公开(公告)号：US08458426B2

    公开(公告)日：2013-06-04

    申请号：US11624966

    申请日：2007-01-19

    申请人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  Nancy D. Dillon

    发明人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon

    IPC分类号： G06F12/00

    CPC分类号： G06F13/405 ,  G06F13/4022 ,  G06F13/4243

    摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

    摘要翻译： 在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。 第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。 重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

    Transceiver with latency alignment circuitry
    4.
    发明申请
    Transceiver with latency alignment circuitry 有权
    具有延迟对准电路的收发器

    公开(公告)号：US20050149685A1

    公开(公告)日：2005-07-07

    申请号：US11058333

    申请日：2005-02-15

    申请人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

    发明人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/405 ,  G06F13/4022 ,  G06F13/4243

    摘要： A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.

    摘要翻译： 收发机包括第一接口，用于通过第一信道从存储器装置接收第一信号。 发射机通过第二信道将表示第一信号的第二信号发送到主设备。 多个寄存器存储由主设备提供的多个值。 多个值包括第一值，该第一值指定由发送器向主设备发送的第二信号的发送定时调整。

    Pulse control for nonvolatile memory
    6.
    发明授权
    Pulse control for nonvolatile memory 有权
    非易失性存储器的脉冲控制

    公开(公告)号：US08644078B2

    公开(公告)日：2014-02-04

    申请号：US13146521

    申请日：2010-01-29

    申请人： Mark D. Kellam ,  Brent Steven Haukness ,  Gary B. Bronner ,  Kevin Donnelly

    发明人： Mark D. Kellam ,  Brent Steven Haukness ,  Gary B. Bronner ,  Kevin Donnelly

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0408 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3459

    摘要： A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

    摘要翻译： 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

    TRANSCEIVER WITH SELECTABLE DATA RATE
    7.
    发明申请
    TRANSCEIVER WITH SELECTABLE DATA RATE 有权
    具有可选数据速率的收发器

    公开(公告)号：US20070147569A1

    公开(公告)日：2007-06-28

    申请号：US11685017

    申请日：2007-03-12

    申请人： Kun-Yung Chang ,  Kevin Donnelly

    发明人： Kun-Yung Chang ,  Kevin Donnelly

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0337 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025

    摘要： An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal. A select circuit selects, according to a transmit data rate select signal, data bits within an outbound data value to form the parallel set of bits received within the serializing circuit. Bits within the outbound data value are selected to achieve a first data rate when the transmit data rate select signal is in a first state, and to achieve a second data rate when the transmit data rate select signal is in a second state.

    摘要翻译： 一种具有可选数据速率时钟数据恢复（CDR）电路和可选数据速率发射电路的集成电路装置。 CDR电路包括在第一时钟信号的周期期间捕获输入信号的多个采样的接收电路。 选择电路耦合到接收电路，以根据接收数据速率选择信号选择多个采样中的一个作为输入信号的第一选定采样，并将多个样本中的另一个作为第二选定采样 的输入信号。 相位控制电路被耦合以接收输入信号的第一和第二选定采样，并且包括用于比较所选择的采样以确定第一时钟信号是否导通或滞后输入信号的转换的电路。 发送电路包括串行电路，用于接收并行的一组位，并且响应于第一时钟信号而将该组比特顺序地输出到输出驱动器。 选择电路根据发送数据速率选择信号选择出站数据值内的数据位，以形成在串行化电路内接收的并行的一组位。 当发送数据速率选择信号处于第一状态时，选择出站数据值内的比特以实现第一数据速率，并且当发送数据速率选择信号处于第二状态时获得第二数据速率。

    Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data
    10.
    发明授权
    Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data 有权
    时钟数据恢复（“CDR”）电路，可变频率数据的装置和方法

    公开(公告)号：US08130891B2

    公开(公告)日：2012-03-06

    申请号：US12710250

    申请日：2010-02-22

    申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

    发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

    摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

    摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的失调逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。 在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。