公开(公告)号：US20140008796A1

公开(公告)日：2014-01-09

申请号：US13934485

申请日：2013-07-03

Applicant: Keun-Ho CHOI

Inventor： Keun-Ho CHOI

IPC: H01L23/522

CPC classification number: H01L23/5221 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/4941 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/48145 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05599

Abstract: A semiconductor package includes a mounting board including a bonding pad, first and second semiconductor chips sequentially stacked on the mounting board, a first wire connecting a first region of the bonding pad to a chip pad of the first semiconductor chip, and a second wire connecting the first region of the bonding pad to a chip pad of the second semiconductor chip, the second wire having a reverse loop configuration.

Abstract translation: 半导体封装包括安装板，其包括接合焊盘，顺序地堆叠在安装板上的第一和第二半导体芯片，将焊盘的第一区域连接到第一半导体芯片的芯片焊盘的第一引线和连接 所述接合焊盘的第一区域到所述第二半导体芯片的芯片焊盘，所述第二引线具有反向回路配置。

公开(公告)号：US20140374893A1

公开(公告)日：2014-12-25

申请号：US14225410

申请日：2014-03-25

Applicant: KEUN HO CHOI

Inventor： KEUN HO CHOI

IPC: H01L23/48 ,  H01L23/495

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package, comprising: a package substrate including chip regions, a separation region between the chip regions, and an edge region around the chip and separation regions; semiconductor chips disposed on the chip regions of the package substrate; and signal patterns. The package substrate comprises an upper layer substantially adjacent to the semiconductor chips, a lower layer including interconnection structures disposed in the chip regions, and an intermediate layer between the upper and lower layers, the intermediate layer includes through holes disposed only outside of the separation region; and the signal patterns are in contact with the interconnection structures through the through holes.

Abstract translation: 一种半导体封装，包括：封装衬底，其包括芯片区域，所述芯片区域之间的分离区域和所述芯片周围的边缘区域和分离区域; 设置在封装基板的芯片区域上的半导体芯片; 和信号模式。 封装基板包括与半导体芯片基本相邻的上层，包括布置在芯片区域中的互连结构的下层以及上层和下层之间的中间层，中间层包括仅设置在分离区域外侧的通孔 ; 并且信号图案通过通孔与互连结构接触。

公开(公告)号：US20100314740A1

公开(公告)日：2010-12-16

申请号：US12776789

申请日：2010-05-10

Applicant: Keun-ho CHOI ,  Myung-kee CHUNG ,  Kun-dae YEOM ,  Kil-soo KIM

Inventor： Keun-ho CHOI ,  Myung-kee CHUNG ,  Kun-dae YEOM ,  Kil-soo KIM

IPC: H01L25/065 ,  H01L23/52

CPC classification number: H01L23/3128 ,  H01L23/3121 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multi-chip package device can include a plurality of integrated circuit device chips stacked on one another inside a multi-chip package including the device. The device can include an electrically isolated multi-chip support structure that is directly connected to first and second electrically active integrated circuit structures via respective first and second adhesive layers located on opposing sides of the electrically isolated multi-chip support structure.

Abstract translation: 多芯片封装器件可以包括在包括该器件的多芯片封装内彼此堆叠的多个集成电路器件芯片。 该装置可以包括电隔离的多芯片支撑结构，其通过位于电隔离的多芯片支撑结构的相对侧上的相应的第一和第二粘合层直接连接到第一和第二电活动集成电路结构。

公开(公告)号：US09111913B2

公开(公告)日：2015-08-18

申请号：US14225410

申请日：2014-03-25

Applicant: Keun Ho Choi

Inventor： Keun Ho Choi

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/02 ,  H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package, comprising: a package substrate including chip regions, a separation region between the chip regions, and an edge region around the chip and separation regions; semiconductor chips disposed on the chip regions of the package substrate; and signal patterns. The package substrate comprises an upper layer substantially adjacent to the semiconductor chips, a lower layer including interconnection structures disposed in the chip regions, and an intermediate layer between the upper and lower layers, the intermediate layer includes through holes disposed only outside of the separation region; and the signal patterns are in contact with the interconnection structures through the through holes.

Abstract translation: 一种半导体封装，包括：封装衬底，其包括芯片区域，所述芯片区域之间的分离区域和所述芯片周围的边缘区域和分离区域; 设置在封装基板的芯片区域上的半导体芯片; 和信号模式。 封装基板包括与半导体芯片基本相邻的上层，包括布置在芯片区域中的互连结构的下层以及上层和下层之间的中间层，中间层包括仅设置在分离区域外侧的通孔 ; 并且信号图案通过通孔与互连结构接触。