公开(公告)号：US06191903B1

公开(公告)日：2001-02-20

申请号：US09132637

申请日：1998-08-11

申请人： Kensuke Fujimoto ,  Masahiro Shigenobu ,  Hideki Mawatari

发明人： Kensuke Fujimoto ,  Masahiro Shigenobu ,  Hideki Mawatari

IPC分类号： G11B509

CPC分类号： G11B20/00927 ,  G11B20/00086 ,  G11B20/1252 ,  G11B27/3027 ,  G11B2020/1476 ,  G11B2220/2562 ,  H04N5/85 ,  H04N9/8042 ,  H04N9/8063

摘要： This invention relates to a recording medium, data transmission apparatus, data receiver, and optical disk unit, and particularly applies to a system which transmits video data and other data or records them on an optical disk in a predetermined block unit, and permits each frame to be easily and correctly located by low volumes of identification data. At least contiguous synchronization patterns or/and contiguous synchronization patterns with one synchronization pattern interleaved therebetween are assigned with unique combinations.

摘要翻译： 本发明涉及一种记录介质，数据传输装置，数据接收器和光盘单元，特别适用于以预定块单元传输视频数据和其他数据或将其记录在光盘上的系统，并且允许每个帧 通过低容量的识别数据容易且正确地定位。 具有在其间交错的一个同步模式的至少连续同步模式或/或连续的同步模式被赋予独特的组合。

公开(公告)号：US6148043A

公开(公告)日：2000-11-14

申请号：US972936

申请日：1997-11-18

申请人： Kensuke Fujimoto

发明人： Kensuke Fujimoto

IPC分类号： G11B20/18 ,  G11B7/0045 ,  H03M13/23 ,  H03M13/41 ,  H04L1/00 ,  H04L25/08 ,  H04L27/06

CPC分类号： H03M13/4107 ,  H03M13/3961 ,  H03M13/6502 ,  G11B20/10101 ,  G11B7/00456

摘要： In a branch metric calculating circuit, using a sample value `y` input from an A/D converter and reference levels {-1, -1/2, 1/2, 1}, branch metric calculation is performed by squaring a difference between the sample value `y` and each of the reference levels and subtracting the square of the sample value `y` from the resultant value of squaring the difference. Since actual calculation is carried out for values 2y, y-3/4, -y-3/4 and -2y in this arrangement, square operation circuits can be eliminated, thereby making it possible to simplify a configuration of a Viterbi decoder.

摘要翻译： 在分支度量计算电路中，使用从A / D转换器输入的采样值“y”和参考电平{-1，+ E，fra 1/2 + EE，+ E，fra 1/2 + EE，1 }，通过对采样值“y”和每个参考电平之间的差进行平方，并从所得到的差的平方值中减去采样值“y”的平方，执行支路量度计算。 由于在这种布置中对于值2y，y- + E，fra 3/4 + EE，-y- + E，fra 3/4 + EE和-2y进行实际计算，所以可以消除平方运算电路， 可以简化维特比解码器的配置。

公开(公告)号：US5917792A

公开(公告)日：1999-06-29

申请号：US886343

申请日：1997-07-01

申请人： Masahiro Shigenobu ,  Kensuke Fujimoto

发明人： Masahiro Shigenobu ,  Kensuke Fujimoto

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30 ,  G11B7/00

CPC分类号： G11B20/1217 ,  G11B20/1833 ,  G11B27/3027 ,  G11B2220/216 ,  G11B2220/2525 ,  G11B2220/2562 ,  G11B2220/2575

摘要： An ECC encoder adds sync patterns to a preamble part and a data part in respectively different sequences. A modulator modulates data to which sync patterns have been added by the ECC encoder, and the result is recorded on an optical disk. The playback RF signal output by the optical disk is demodulated by a demodulator, and the sync patterns inserted in the signal are detected. From the combinations of detected sync patterns, the demodulator 12 identifies whether a currently reproduced frame is the preamble part or the data part, and from the identification result, playback data is sequentially stored in a predetermined area of a SRAM. It is thus performed to identify a preamble part from a reproduced RF signal, and accurately extract one block of data.

摘要翻译： ECC编码器将同步模式分别以不同的顺序添加到前同步码部分和数据部分。 调制器调制由ECC编码器添加了同步模式的数据，并将结果记录在光盘上。 由光盘输出的重放RF信号由解调器解调，并且检测插入在信号中的同步图案。 从检测到的同步模式的组合中，解调器12识别当前再现的帧是前同步码部分还是数据部分，并且根据识别结果，重放数据被顺序存储在SRAM的预定区域中。 因此，执行从再现的RF信号识别前导码部分，并且准确地提取一个数据块。

公开(公告)号：US5848047A

公开(公告)日：1998-12-08

申请号：US887519

申请日：1997-07-03

申请人： Kensuke Fujimoto

发明人： Kensuke Fujimoto

IPC分类号： G11B20/14 ,  G11B20/18 ,  H03L7/06 ,  H03L7/091 ,  H03L7/099 ,  H04L7/033 ,  G11B7/00 ,  H03L7/08

CPC分类号： G11B20/10037 ,  G11B20/1403 ,  G11B20/1876 ,  H03L7/091 ,  H03L7/0994

摘要： An A/D converter supplies an interpolation circuit with sampled values which are obtained by sampling a playback signal coming from a read-out device in synchronization with a system clock signal. In the interpolation circuit, the value of the playback signal at the time the phase of a PLL clock phase signal P supplied by a PLL clockphase signal generator becomes zero is computed from the sampled values by using a linear interpolation technique. The interpolation value is then supplied to a binary conversion circuit and fed back to a phase error detecting circuit. The binary conversion circuit converts the interpolation value of the playback signal into a binary value which is then supplied to a circuit at the following stage. The phase error detecting circuit detects a zero cross of the interpolation value of the playback signal. The zero cross timing is then used for computing a phase error signal which is then output to the PLL clock phase signal generator by way of a loop filter. The PLL clock phase signal generator generates the PLL clock phase signal P which is supplied to the interpolation circuit as described above.

摘要翻译： A / D转换器向内插电路提供与系统时钟信号同步地对来自读出装置的重放信号进行采样而获得的采样值。 在内插电路中，通过使用线性内插技术，根据采样值来计算由PLL时钟相位信号发生器提供的PLL时钟相位信号P的相位为零时的重放信号的值。 然后将内插值提供给二进制转换电路并反馈到相位误差检测电路。 二进制转换电路将重放信号的内插值转换为二进制值，然后将其提供给下一级的电路。 相位误差检测电路检测回放信号的内插值的零交叉。 然后将零交叉定时用于计算相位误差信号，然后通过环路滤波器输出到PLL时钟相位信号发生器。 如上所述，PLL时钟相位信号发生器产生提供给插值电路的PLL时钟相位信号P.

公开(公告)号：US5841323A

公开(公告)日：1998-11-24

申请号：US938320

申请日：1997-09-26

申请人： Kensuke Fujimoto

发明人： Kensuke Fujimoto

IPC分类号： G11B20/14 ,  H03L7/06 ,  H03L7/085 ,  H03L7/113 ,  H03L7/087

CPC分类号： H03L7/113 ,  H04L7/0004 ,  H04L7/033

摘要： An A/D converter performs sampling of a reproduced signal from a reading device in synchronism with a clock signal from a PLL circuit and outputs the sampled value to a binary circuit and a phase comparator. The phase comparator detects a change from a positive sampled value to a negative one or from the negative sampled value to a positive one (zero-cross) and outputs a phase error signal corresponding to the zero-cross to a frequency comparator. The frequency comparator outputs a frequency error sensed in reference to a variation of the phase error signal to a switch through a low pass filter. The switch outputs the frequency error to an adder only when the PLL is not in a lock state. The adder outputs a sum of the frequency error and the phase error to a VCO through a loop filter. The VCO generates the clock signal with a frequency corresponding to the sum and supplies it to the A/D converter.

摘要翻译： A / D转换器与来自PLL电路的时钟信号同步地从读取装置执行再现信号的采样，并将采样值输出到二进制电路和相位比较器。 相位比较器检测从正采样值到负采样值或从负采样值到正采样值（零交叉）的变化，并将与过零相对应的相位误差信号输出到频率比较器。 频率比较器通过低通滤波器将与参考相位误差信号的变化相关的频率误差输出到开关。 只有当PLL不处于锁定状态时，开关才将频率误差输出到加法器。 加法器通过环路滤波器将频率误差和相位误差的和输出到VCO。 VCO产生具有对应于和的频率的时钟信号，并将其提供给A / D转换器。

公开(公告)号：US07200094B2

公开(公告)日：2007-04-03

申请号：US11113557

申请日：2005-04-25

申请人： Kensuke Fujimoto ,  Shunji Yoshimura ,  Atsushi Fukumoto ,  Yasuhito Tanaka

发明人： Kensuke Fujimoto ,  Shunji Yoshimura ,  Atsushi Fukumoto ,  Yasuhito Tanaka

IPC分类号： G11B5/76

CPC分类号： G11B20/10009 ,  G11B7/005 ,  G11B7/1267 ,  G11B11/10515 ,  G11B11/1053 ,  G11B11/10595 ,  G11B20/10 ,  G11B20/18 ,  G11B20/1833 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343

摘要： The present invention provides an apparatus and a method for precisely and adequately evaluating actual quality of reproduced data whenever applying a maximum likelihood decoder for converting signal reproduced from a recording medium into binary signal Based on data arrays of a pair of binary data outputted from a “Viterbi” decoder, SAM values are secured by selecting any of path-metric differential values (00) and (11) being the difference between a pair of values compared when renewing path-metric values PMM (00) and (11) outputted from the “Viterbi” decoder. The minimum SAM value for an ideally-reproduced signal is outputted from a constant generating circuit. If the SAM values are verified as valid, and yet, if the SAM values coincide with the equation “input SAM values”≦“data value outputted from the constant generating circuit”, then squared values outputted from a square circuit are averaged by an averaging circuit. Finally, the average value is outputted as the reproduced signal evaluation.

摘要翻译： 本发明提供了一种用于在将用于将从记录介质再现的信号转换为二进制信号的最大似然解码器的情况下精确地和适当地评估再现数据的实际质量的装置和方法。基于从“ 维特比“解码器，通过选择路径度量差分值（00）和（11）中的任何一个来确保SAM值，所述差分值是当从更新路由度量值PMM（00）和（11）更新时比较的一对值之间的差 “维特比”解码器。 理想再现信号的最小SAM值从恒定发生电路输出。 如果SAM值被验证为有效，然而，如果SAM值与从常数产生电路输出的等式“输入SAM值”<=“数据值”一致，则从平方电路输出的平方值由 平均电路。 最后，平均值作为再现信号评估输出。

公开(公告)号：US20060215513A1

公开(公告)日：2006-09-28

申请号：US10541445

申请日：2003-12-10

申请人： Takashi Fujimoto ,  Masahiro Shigenobu ,  Kenichiro Aridome ,  Yasuaki Maeda ,  Kensuke Fujimoto ,  Hideki Mawatari

发明人： Takashi Fujimoto ,  Masahiro Shigenobu ,  Kenichiro Aridome ,  Yasuaki Maeda ,  Kensuke Fujimoto ,  Hideki Mawatari

IPC分类号： G11B7/12

CPC分类号： G11B7/126 ,  G11B7/0045

摘要： The present invention relates to an optical recording method for recording data on an optical disc by using a laser beam. When the optical disc is inserted into an optical recording device (step S1), a test writing area PCA (Power Calibration Area) that can be used for an OPC (Optimum Power Calibration) on the optical disc is searched and an optical pickup is allowed to stand by at that position (step S4). Then, when an input of a recording operation of data is received (step S6), an OPC operation is carried out at the stand-by position (step S7). After an optimum power is obtained, the optical pickup is moved to a data recording area on the optical disc (step S10) to record the data in the data recording area of the optical disc by the optical pickup (step S11).

摘要翻译： 本发明涉及一种通过使用激光束在光盘上记录数据的光记录方法。 当将光盘插入到光学记录装置中时（步骤S1），搜索可用于光盘上的OPC（最佳功率校准）的测试写入区域PCA（功率校准区域），并且光学拾取器 允许在该位置待命（步骤S4）。 然后，当接收到数据的记录操作的输入时（步骤S6），在待机位置执行OPC操作（步骤S7）。 在获得最佳功率之后，将光学拾取器移动到光盘上的数据记录区域（步骤S10），以通过光学拾取器将数据记录在光盘的数据记录区域中（步骤S11）。

公开(公告)号：US5987082A

公开(公告)日：1999-11-16

申请号：US889743

申请日：1997-07-10

申请人： Kensuke Fujimoto

发明人： Kensuke Fujimoto

IPC分类号： G01R25/00 ,  G11B20/10 ,  G11B20/14 ,  H03H17/00 ,  H03L7/085 ,  H04L7/00

CPC分类号： G11B20/1403 ,  G11B20/10009

摘要： To reduce a data-error rate caused by interpolation errors. An adder computes the sum of a sampled value Si+1 of a playback signal and a value 8.times.Si+1 produced by a bit shifter to output the sum 9.times.Si+1 to an adder. The adder adds the sum (9.times.Si+1) supplied thereto by the adder to a sum (9.times.Si) supplied thereto after being delayed by a delay element and outputs the result of the addition (9.times.Si+9.times.Si+1) to an adder. An adder computes the sum of a sampled value Si-1 supplied thereto after being delayed by delay elements and a sampled value Si+2 supplied thereto by an A/D converter and outputs sum (Si-1+Si+2) to the adder. The adder which is used as a subtractor computes the difference between the sum (9.times.Si+9.times.Si+1) supplied thereto by the adder and the sum (Si-1+Si+2) supplied thereto by the adder and outputs the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) to a bit shifter. The bit shifter shifts the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) supplied thereto by the adder by four bits toward the LSB and outputs the right-shifted value (Si-1-9.times.Si-9.times.Si+1+Si+2)/16 to a second interpolation circuit as a first interpolation value Si' along with the sampled values Si and Si+1. As a result, the number of sampled values seemingly appears increased.

摘要翻译： 减少由插补误差引起的数据错误率。 加法器计算重放信号的采样值Si + 1和由比特移位器产生的值8xSi + 1的和，以将和9xSi + 1输出到加法器。 加法器将由加法器提供的和（9xSi + 1）加到由延迟元件延迟后提供给它的和（9xSi），并将相加结果（9xSi + 9xSi + 1）输出到加法器。 加法器计算由延迟元件延迟后提供给其的采样值Si-1和由A / D转换器提供给其的采样值Si + 2的和，并将加法（Si-1 + Si + 2）加到加法器 。 用作减法器的加法器计算由加法器提供给它的和（9xSi + 9xSi + 1）与由加法器提供给它的和（Si-1 + Si + 2）之间的差值，并输出差值（Si- 1-9xSi-9xSi + 1 + Si + 2）到位移位器。 位移器将由加法器提供给其的差（Si-1-9xSi-9xSi + 1 + Si + 2）向LSB移位四位，并输出右移位值（Si-1-9xSi-9xSi + 1 + Si + 2）/ 16连接到作为第一插值值Si'的第二插值电路以及采样值Si和Si + 1。 因此，采样值的数量看起来似乎增加了。

公开(公告)号：US6128256A

公开(公告)日：2000-10-03

申请号：US313491

申请日：1999-05-17

申请人： Koji Inoue ,  Kensuke Fujimoto ,  Masahiro Shigenobu

发明人： Koji Inoue ,  Kensuke Fujimoto ,  Masahiro Shigenobu

IPC分类号： G11B7/007 ,  G11B7/085 ,  G11B11/105 ,  G11B21/08 ,  G11B27/10 ,  G11B27/19 ,  G11B27/24 ,  G11B27/30 ,  G11B17/22

CPC分类号： G11B7/08505 ,  G11B21/083 ,  G11B27/105 ,  G11B27/19 ,  G11B27/24 ,  G11B7/00745 ,  G11B7/08529 ,  G11B11/10565 ,  G11B27/3027 ,  G11B7/08541

摘要： An apparatus and method are provided for locating a desired track on a disk shaped recording medium. The disk has a first pre-group and a second pre-group. At least one of the pre-groups has encoded address information shared by at least one track on the inner side of the pre-group, and shared by at least one track on an outer side of the pre-group. A desired track is located based on changes in address information detected during or after a track jump.

摘要翻译： 提供了一种用于将期望的轨道定位在盘形记录介质上的装置和方法。 磁盘具有第一个预组和第二个预组。 预组中的至少一个已经编码了由前组的内侧上的至少一个轨道共享的地址信息，并且由前组的外侧上的至少一个轨道共享。 基于在轨道跳跃期间或之后检测到的地址信息的变化来定位期望的轨道。

公开(公告)号：US06940800B2

公开(公告)日：2005-09-06

申请号：US10017156

申请日：2001-12-14

申请人： Kensuke Fujimoto ,  Shunji Yoshimura ,  Atsushi Fukumoto ,  Yasuhito Tanaka

发明人： Kensuke Fujimoto ,  Shunji Yoshimura ,  Atsushi Fukumoto ,  Yasuhito Tanaka

IPC分类号： G11B7/0045 ,  G11B7/005 ,  G11B20/10 ,  G11B20/18 ,  H03M13/39 ,  H03M13/41 ,  G11B5/76

CPC分类号： G11B20/10009 ,  G11B7/005 ,  G11B7/1267 ,  G11B11/10515 ,  G11B11/1053 ,  G11B11/10595 ,  G11B20/10 ,  G11B20/18 ,  G11B20/1833 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343

摘要： The present invention provides an apparatus and a method for precisely and adequately evaluating actual quality of reproduced data whenever applying a maximum likelihood decoder for converting signal reproduced from a recording medium into binary signal. Based on data arrays of a pair of binary data outputted from a “Viterbi” decoder, SAM values are secured by selecting any of path-metric differential values (00) and (11) being the difference between a pair of values compared when renewing path-metric values PMM (00) and (11) outputted from the “Viterbi” decoder. The minimum SAM value for an ideally-reproduced signal is outputted from a constant generating circuit. If the SAM values are verified as valid, and yet, if the SAM values coincide with the equation “input SAM values”≦“data value outputted from the constant generating circuit”, then squared values outputted from a square circuit are averaged by an averaging circuit. Finally, the average value is outputted as the reproduced signal evaluation.

摘要翻译： 本发明提供了一种用于在应用用于将从记录介质再现的信号转换成二进制信号的最大似然解码器时，精确且充分地评估再现数据的实际质量的装置和方法。 基于从“维特比”解码器输出的一对二进制数据的数据阵列，通过选择路径度量差分值（00）和（11）中的任一个作为在更新路径上比较的一对值之间的差异来确保SAM值 从“维特比”解码器输出的测量值PMM（00）和（11）。 理想再现信号的最小SAM值从恒定发生电路输出。 如果SAM值被验证为有效，然而，如果SAM值与从常数产生电路输出的等式“输入SAM值”<=“数据值”一致，则从平方电路输出的平方值由 平均电路。 最后，平均值作为再现信号评估输出。