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    SOI transistors with improved source/drain structures with enhanced strain
    1.
    发明授权
    SOI transistors with improved source/drain structures with enhanced strain 有权
    具有改善的源/漏结构的SOI晶体管具有增强的应变

    公开(公告)号：US09263345B2

    公开(公告)日：2016-02-16

    申请号：US13451696

    申请日：2012-04-20

    申请人： Ken-Ichi Goto ,  Dhanyakumar Mahaveer Sathaiya ,  Ching-Chang Wu ,  Tzer-Min Shen

    发明人： Ken-Ichi Goto ,  Dhanyakumar Mahaveer Sathaiya ,  Ching-Chang Wu ,  Tzer-Min Shen

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L29/66 ,  H01L27/12 ,  H01L29/165 ,  H01L21/38

    CPC分类号： H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    摘要： A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance.

    摘要翻译： 提供了具有改进的器件性能的晶体管结构及其形成方法。 晶体管结构是SOI（绝缘体上硅）晶体管。 在一个实施例中，氧化物层上的硅层是相对均匀的膜，在另一个实施例中，氧化物层上的硅层是硅片。 晶体管器件包括由延伸穿过硅层的应变材料形成的源极/漏极结构，穿过氧化物层并进入可能是硅的下面的衬底。 源极/漏极结构还包括在硅层的上表面上方延伸的部分，从而提供增加的应变层的体积以提供附加的载流子迁移率和更高的性能。

    FinFET method and structure with embedded underlying anti-punch through layer
    4.
    发明授权
    FinFET method and structure with embedded underlying anti-punch through layer 有权
    FinFET方法和结构具有嵌入式底层抗穿透层

    公开(公告)号：US08497171B1

    公开(公告)日：2013-07-30

    申请号：US13541806

    申请日：2012-07-05

    申请人： Wei-Hao Wu ,  Kai-Chieh Yang ,  Wen-Hsing Hsieh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    发明人： Wei-Hao Wu ,  Kai-Chieh Yang ,  Wen-Hsing Hsieh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823821

    摘要： Methods and structures for forming semiconductor FinFET devices with superior repeatability and reliability include providing APT (anti-punch through) layer accurately formed beneath a semiconductor fins, are provided. Both the n-type and p-type APT layers are formed prior to the formation of the material from which the semiconductor fin is formed. In some embodiments, barrier layers are added between the accurately positioned APT layer and the semiconductor fin. Ion implantation methods and epitaxial growth methods are used to form appropriately doped APT layers in a semiconductor substrate surface. The fin material is formed over the APT layers using epitaxial growth/deposition methods.

    摘要翻译： 用于形成具有优异重复性和可靠性的半导体FinFET器件的方法和结构包括提供准确地形成在半导体鳍片之下的APT（抗穿通）层。 在形成半导体翅片的材料形成之前，形成n型和p型APT层。 在一些实施例中，在精确定位的APT层和半导体鳍片之间添加阻挡层。 使用离子注入方法和外延生长方法在半导体衬底表面中形成适当掺杂的APT层。 使用外延生长/沉积方法在APT层上形成翅片材料。

    Tunnel Field-Effect Transistors with Superlattice Channels
    5.
    发明申请
    Tunnel Field-Effect Transistors with Superlattice Channels 有权
    具超晶格通道的隧道场效应晶体管

    公开(公告)号：US20110027959A1

    公开(公告)日：2011-02-03

    申请号：US12898421

    申请日：2010-10-05

    申请人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

    发明人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7391 ,  H01L21/26586

    摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

    摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

    Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling
    6.
    发明申请
    Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling 有权
    具有窄带隙通道和强栅耦合的隧道场效应晶体管

    公开(公告)号：US20090026553A1

    公开(公告)日：2009-01-29

    申请号：US11828211

    申请日：2007-07-25

    申请人： Krishna Kumar Bhuwalka ,  Ken-Ichi Goto

    发明人： Krishna Kumar Bhuwalka ,  Ken-Ichi Goto

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66545 ,  H01L29/66356 ,  H01L29/7391

    摘要： A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.

    摘要翻译： 提供半导体器件及其形成方法。 半导体器件包括：包含半导体材料的低能带隙层; 低能带隙层上的栅极电介质; 位于栅极电介质上的栅电极; 邻近所述栅极电介质的第一源极/漏极区域，其中所述第一源极/漏极区域是第一导电类型; 以及与栅极电介质相邻的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 低能带隙层位于第一和第二源极/漏极区之间。

    Multi-gate semiconductor devices
    7.
    发明授权
    Multi-gate semiconductor devices 有权
    多栅极半导体器件

    公开(公告)号：US08987824B2

    公开(公告)日：2015-03-24

    申请号：US13301873

    申请日：2011-11-22

    申请人： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih-Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    发明人： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih-Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10

    CPC分类号： H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

    摘要： A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

    摘要翻译： 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。

    Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling
    10.
    发明授权
    Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling 有权
    隧道场效应晶体管具有窄带隙通道和强栅耦合

    公开(公告)号：US08354695B2

    公开(公告)日：2013-01-15

    申请号：US12880236

    申请日：2010-09-13

    申请人： Krishna Kumar Bhuwalka ,  Ken-Ichi Goto

    发明人： Krishna Kumar Bhuwalka ,  Ken-Ichi Goto

    IPC分类号： H01L29/161 ,  H01L29/78

    CPC分类号： H01L29/66545 ,  H01L29/66356 ,  H01L29/7391

    摘要： A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.

    摘要翻译： 提供半导体器件及其形成方法。 半导体器件包括：包含半导体材料的低能带隙层; 低能带隙层上的栅极电介质; 位于栅极电介质上的栅电极; 邻近所述栅极电介质的第一源极/漏极区域，其中所述第一源极/漏极区域是第一导电类型; 以及与栅极电介质相邻的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 低能带隙层位于第一和第二源极/漏极区之间。