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    Semiconductor Memory Devices Having Strapping Contacts
    1.
    发明申请
    Semiconductor Memory Devices Having Strapping Contacts 有权
    具有捆扎触头的半导体存储器件

    公开(公告)号：US20130187119A1

    公开(公告)日：2013-07-25

    申请号：US13630505

    申请日：2012-09-28

    Applicant: Jung-in Kim ,  Jae-hee Oh ,  Jun-hyok Kong ,  Sung-ho Eun ,  Yong-tae Oh

    Inventor： Jung-in Kim ,  Jae-hee Oh ,  Jun-hyok Kong ,  Sung-ho Eun ,  Yong-tae Oh

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  G11C5/06 ,  G11C8/10 ,  G11C11/16 ,  G11C13/0004 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. The active patterns contact the first interconnection lines through strapping contacts in the strapping regions.

    Abstract translation: 提供了具有捆扎触点的半导体存储器件，器件包括在第一方向上的相邻单元区域之间的单元区域和绑带区域。 在整个单元区域和捆扎区域中沿着第一方向延伸的活动图案在与第一方向相交的第二方向上彼此间隔开。 在整个单元区域和捆扎区域沿第一方向延伸的第一互连线在第二方向上彼此间隔开，同时与有源图案重叠。 沿第二方向延伸的第二互连线与单元区域中的有源图案和第一互连线相交。 第二互连线在第一方向上彼此间隔开。 存储单元位于单元区域中的第一和第二互连线的交叉部分处。 有源图案通过捆扎区域中的捆扎触头接触第一互连线。

    Method Of Forming Pattern Structure And Method Of Fabricating Semiconductor Device Using The Same
    2.
    发明申请
    Method Of Forming Pattern Structure And Method Of Fabricating Semiconductor Device Using The Same 有权
    形成图案结构的方法及使用其制造半导体器件的方法

    公开(公告)号：US20110207285A1

    公开(公告)日：2011-08-25

    申请号：US13029449

    申请日：2011-02-17

    Applicant: Jung-In Kim ,  Jaehee Oh ,  Kiseok Suh

    Inventor： Jung-In Kim ,  Jaehee Oh ,  Kiseok Suh

    IPC: H01L21/02 ,  H01L21/027

    CPC classification number: H01L27/24 ,  H01L21/31144

    Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

    Abstract translation: 提供一种形成图案结构的方法和使用该图案结构制造半导体器件的方法，形成图案结构的方法包括在形成在下层上的下层上形成掩模。 使用掩模作为蚀刻掩模蚀刻下层，从而在下层上形成图案。 模式至少定义一个开口。 在开口中形成牺牲层，并且去除掩模。 当去除掩模时，开口中的牺牲层被部分蚀刻。

    Method of forming memory device
    6.
    发明授权
    Method of forming memory device 有权
    形成存储器件的方法

    公开(公告)号：US08518790B2

    公开(公告)日：2013-08-27

    申请号：US13692329

    申请日：2012-12-03

    Applicant: Jung-in Kim ,  Jae-Hee Oh ,  Hyunho Kim ,  Ji-Hyun Jeong

    Inventor： Jung-in Kim ,  Jae-Hee Oh ,  Hyunho Kim ,  Ji-Hyun Jeong

    IPC: H01L21/02

    CPC classification number: H01L45/16 ,  H01L27/1021 ,  H01L27/24

    Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.

    Abstract translation: 一种可变电阻存储器件及其形成方法。 该方法可以包括在衬底上形成下电极，在衬底上堆叠第一蚀刻停止层和第二蚀刻停止层，在第二蚀刻停止层上形成绝缘层，形成凹陷区域以通过图案曝光下电极 绝缘层和第一和第二蚀刻停止层，在凹陷区域中形成可变电阻材料层，并在可变电阻材料层上形成上电极。 第一蚀刻停止层可以相对于第二蚀刻停止层具有蚀刻选择性。

    Frequency synchronization apparatus and method in OFDM system
    7.
    发明授权
    Frequency synchronization apparatus and method in OFDM system 失效
    OFDM系统中的频率同步装置和方法

    公开(公告)号：US08275059B2

    公开(公告)日：2012-09-25

    申请号：US12477269

    申请日：2009-06-03

    Applicant: Bon Young Koo ,  Hyung Jin Choi ,  Se Bin Im ,  Jung In Kim

    Inventor： Bon Young Koo ,  Hyung Jin Choi ,  Se Bin Im ,  Jung In Kim

    IPC: H04L27/28

    CPC classification number: H04L27/2657 ,  H04L27/2676 ,  H04L27/2688

    Abstract: A frequency synchronization apparatus includes: a correlating unit that obtains a first correlation value by correlating a known reference guard interval of an OFDM symbol and a reference copy interval corresponding to the reference guard interval, and obtains a second correlation value by correlating the estimate guard interval and an estimate copy interval corresponding to the estimate guard interval; a determining unit that compares the first and second correlation values to determine a first case where the first correlation value is larger by a pre-set magnification than the second correlation value, a second case where the second correlation value is larger by a pre-set magnification than the first correlation value, and a third case which is not the first case nor the second case; and a frequency offset estimating unit that estimates a frequency offset by using a correlation value corresponding to any one of the first to third.

    Abstract translation: 频率同步装置包括：相关单元，通过将OFDM符号的已知参考保护间隔与对应于参考保护间隔的参考复制间隔相关联来获得第一相关值，并且通过将估计保护间隔 以及对应于估计保护间隔的估计复制间隔; 确定单元，其比较所述第一和第二相关值，以确定所述第一相关值比所述第二相关值大预定倍数的第一情况，所述第二相关值大于预设值的第二情况 并且不是第一种情况的第三种情况也不是第二种情况; 以及频率偏移估计单元，其通过使用与第一至第三中的任一个相对应的相关值来估计频率偏移。

    METHOD OF FORMING MEMORY DEVICE
    8.
    发明申请
    METHOD OF FORMING MEMORY DEVICE 有权
    形成存储器件的方法

    公开(公告)号：US20100227449A1

    公开(公告)日：2010-09-09

    申请号：US12714685

    申请日：2010-03-01

    Applicant: Jung-in KIM ,  Jae-Hee Oh ,  Hyunho Kim ,  Ji-Hyun Jeong

    Inventor： Jung-in KIM ,  Jae-Hee Oh ,  Hyunho Kim ,  Ji-Hyun Jeong

    IPC: H01L21/02

    CPC classification number: H01L45/16 ,  H01L27/1021 ,  H01L27/24

    Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.

    Abstract translation: 一种可变电阻存储器件及其形成方法。 该方法可以包括在衬底上形成下电极，在衬底上堆叠第一蚀刻停止层和第二蚀刻停止层，在第二蚀刻停止层上形成绝缘层，形成凹陷区域以通过图案曝光下电极 绝缘层和第一和第二蚀刻停止层，在凹陷区域中形成可变电阻材料层，并在可变电阻材料层上形成上电极。 第一蚀刻停止层可以相对于第二蚀刻停止层具有蚀刻选择性。

    Method of forming pattern structure and method of fabricating semiconductor device using the same
    9.
    发明授权
    Method of forming pattern structure and method of fabricating semiconductor device using the same 有权
    形成图案结构的方法和使用其制造半导体器件的方法

    公开(公告)号：US08481426B2

    公开(公告)日：2013-07-09

    申请号：US13029449

    申请日：2011-02-17

    Applicant: Jung-In Kim ,  Jaehee Oh ,  Kiseok Suh

    Inventor： Jung-In Kim ,  Jaehee Oh ,  Kiseok Suh

    IPC: H01L21/44 ,  H01L21/461 ,  H01L21/302 ,  H01L21/311 ,  H01L21/469

    CPC classification number: H01L27/24 ,  H01L21/31144

    Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

    Abstract translation: 提供一种形成图案结构的方法和使用该图案结构制造半导体器件的方法，形成图案结构的方法包括在形成在下层上的下层上形成掩模。 使用掩模作为蚀刻掩模蚀刻下层，从而在下层上形成图案。 模式至少定义一个开口。 在开口中形成牺牲层，并且去除掩模。 当去除掩模时，开口中的牺牲层被部分蚀刻。

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