公开(公告)号：US06867495B2

公开(公告)日：2005-03-15

申请号：US09961613

申请日：2001-09-24

Applicant: Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

Inventor： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

IPC: H01L21/22 ,  H01L21/02 ,  H01L21/18 ,  H01L21/20 ,  H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L23/48 ,  H01L27/01 ,  H01L21/76

CPC classification number: H01L21/2253 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76251 ,  H01L29/0615 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  Y10S438/933

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

公开(公告)号：US07605052B2

公开(公告)日：2009-10-20

申请号：US11870564

申请日：2007-10-11

Applicant: Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

Inventor： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

IPC: H01L21/30

CPC classification number: H01L21/2253 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76251 ,  H01L29/0615 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  Y10S438/933

Abstract: A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer on a backside surface of the device wafer of the integrated circuit. Implanting the bond oxide with a diffusing dopant. Diffusing dopant from the bond oxide into the backside surface of the device wafer. Depositing an oxide layer on the bond oxide and bonding the deposited oxide layer to the handle wafer of the integrated circuit.

Abstract translation: 提供了在集成电路中结合到处理晶片的器件晶片氧化物上形成扩散的掺杂​​背面层的方法。 该方法包括在集成电路的器件晶片的背面上形成热粘合氧化物层。 用扩散掺杂剂注入键合氧化物。 将掺杂剂从结合氧化物扩散到器件晶片的背面。 在结合氧化物上沉积氧化物层并将沉积的氧化物层结合到集成电路的处理晶片。

公开(公告)号：US07285475B2

公开(公告)日：2007-10-23

申请号：US11227389

申请日：2005-09-15

Applicant: Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

Inventor： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

IPC: H01L21/30

CPC classification number: H01L21/2253 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76251 ,  H01L29/0615 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  Y10S438/933

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

Abstract translation: 描述了集成电路，半导体器件及其制造方法。 每个实施例在装置晶片中示出了在处理晶片上氧化物结合的扩散的掺杂​​背面层。 扩散层可以源于器件手柄，处理晶片，粘合氧化物或多晶硅或外延硅的附加半导体层。 该方法使用热粘合氧化物或热和沉积氧化物的组合。

公开(公告)号：US07110933B2

公开(公告)日：2006-09-19

申请号：US10628195

申请日：2003-07-28

Applicant: Rex E. Lowther ,  Gregg D. Croft ,  Yiqun Lin ,  Robert Lomenic ,  James P. Furino, Jr. ,  Joseph A. Czagas

Inventor： Rex E. Lowther ,  Gregg D. Croft ,  Yiqun Lin ,  Robert Lomenic ,  James P. Furino, Jr. ,  Joseph A. Czagas

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.

Abstract translation: 使用仿真程序建模金属化寄生效应的方法。 在一个实施例中，公开了一种在电子设计自动化仿真中模拟互连线的方法。 该方法包括将互连线划分成互连线组。 每组互连线不与任何其他互连线组相互作用。 此外，互连线组中的至少一个包含至少三条互连线。 每组中的互连线被建模。 该建模包括至少一个模拟互感和互电容建模。

公开(公告)号：US06362075B1

公开(公告)日：2002-03-26

申请号：US09345261

申请日：1999-06-30

Applicant: Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

Inventor： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

IPC: H01L2100

CPC classification number: H01L21/2253 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76251 ,  H01L29/0615 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  Y10S438/933

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and a deposited oxide.

Abstract translation: 描述了集成电路，半导体器件及其制造方法。 每个实施例在装置晶片中示出了在处理晶片上氧化物结合的扩散的掺杂​​背面层。 扩散层可以源于器件晶片，处理晶片，结合氧化物或多晶硅或外延硅的附加半导体层。 该方法使用热粘合氧化物或热和沉积氧化物的组合。

公开(公告)号：US06946364B2

公开(公告)日：2005-09-20

申请号：US10779121

申请日：2004-02-13

Applicant: Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

Inventor： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

IPC: H01L21/22 ,  H01L21/02 ,  H01L21/18 ,  H01L21/20 ,  H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/30

CPC classification number: H01L21/2253 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76251 ,  H01L29/0615 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  Y10S438/933

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

Abstract translation: 描述了集成电路，半导体器件及其制造方法。 每个实施例在装置晶片中示出了在处理晶片上氧化物结合的扩散的掺杂​​背面层。 扩散层可以源于器件手柄，处理晶片，粘合氧化物或多晶硅或外延硅的附加半导体层。 该方法使用热粘合氧化物或热和沉积氧化物的组合。

公开(公告)号：US06403472B1

公开(公告)日：2002-06-11

申请号：US09339274

申请日：1999-06-23

Applicant: Dustin A. Woodbury ,  Joseph A. Czagas

Inventor： Dustin A. Woodbury ,  Joseph A. Czagas

IPC: H01L214763

CPC classification number: H01L28/20 ,  H01L21/28512 ,  H01L21/28518 ,  Y10S257/914

Abstract: A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling species such as carbon or oxygen are implanted into all contacts. The high resistive contacts are covered with a barrier metal to protect silicide from chemical interaction with the interconnect metalization (aluminum) in the low-resistance contacts. Selective silicide formation converts some of the contacts back to low-resistance contacts.

Abstract translation: 半导体器件或集成电路具有高和低电阻触点。 移动性破坏物质如碳或氧被植入所有触点。 高电阻触点被阻挡金属覆盖，以防止硅化物与低电阻触点中的互连金属化（铝）发生化学相互作用。 选择性硅化物形成将一些触点转换回低电阻触点。

公开(公告)号：US06667523B2

公开(公告)日：2003-12-23

申请号：US10121412

申请日：2002-04-12

Applicant: Dustin A. Woodbury ,  Joseph A. Czagas

Inventor： Dustin A. Woodbury ,  Joseph A. Czagas

IPC: H01L2976

CPC classification number: H01L28/20 ,  H01L21/28512 ,  H01L21/28518 ,  Y10S257/914

Abstract: A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling ions such as carbon are implanted into all contacts of the substrate. High resistive contacts are temporarily covered with an oxide during processing to prevent silicide from forming due to interaction between a siliciding metal and the implanted mobility spoiling ions in the contacts. The resulting high resistance contacts have highly linear I-V curves, even at high voltages. Selective silicide formation converts some of the contacts back to low resistance contacts as a result of interaction between a siliciding metal and the implanted mobility spoiling ions in the low resistance contacts.

公开(公告)号：US06441447B1

公开(公告)日：2002-08-27

申请号：US09367325

申请日：1999-08-11

Applicant: Joseph A. Czagas ,  George Bajor ,  Leonel Enriquez ,  Chris A. McCarty

Inventor： Joseph A. Czagas ,  George Bajor ,  Leonel Enriquez ,  Chris A. McCarty

IPC: H01L2976

CPC classification number: H01L28/20 ,  H01L27/016 ,  H01L27/0802 ,  Y10S257/904

Abstract: A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.

Abstract translation: 通过在覆盖衬底中的集成电路的第一电介质层上直接蚀刻或剥离而形成的第一薄膜电阻器。 第二薄膜电阻器由与第一电阻器不同的材料组成，通过在第一介电层上或在第一介电层上的第二介电层上直接蚀刻或剥离而形成。 第一和第二薄膜电阻器与诸如其它电阻器或集成电路的另一电子器件互连。