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    METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD
    2.
    发明申请
    METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD 有权
    参数化分析与管理方法与系统

    公开(公告)号：US20120227019A1

    公开(公告)日：2012-09-06

    申请号：US13471789

    申请日：2012-05-15

    申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

    发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

    IPC分类号： G06F17/50

    CPC分类号： G01R31/26 ,  G06F17/5045

    摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

    摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

    Multilayer OPC for design aware manufacturing
    3.
    发明授权
    Multilayer OPC for design aware manufacturing 有权
    多层OPC用于设计感知制造

    公开(公告)号：US08214770B2

    公开(公告)日：2012-07-03

    申请号：US12357648

    申请日：2009-01-22

    申请人： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

    发明人： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

    摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

    ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE
    4.
    发明申请
    ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE 失效
    分析多种诱导系统和统计布局对电路性能的依赖性影响

    公开(公告)号：US20120144356A1

    公开(公告)日：2012-06-07

    申请号：US13371537

    申请日：2012-02-13

    申请人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

    发明人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5009 ,  G06F2217/10

    摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

    摘要翻译： 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

    Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells
    6.
    发明授权
    Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells 有权
    基于单个电池的已知多晶硅周边密度布置集成电路设计的方法

    公开(公告)号：US07890906B2

    公开(公告)日：2011-02-15

    申请号：US12117761

    申请日：2008-05-09

    申请人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    发明人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

    摘要翻译： 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

    Integrated circuit with uniform polysilicon perimeter density, method and design structure
    7.
    发明授权
    Integrated circuit with uniform polysilicon perimeter density, method and design structure 有权
    具有均匀多晶硅周密度的集成电路，方法和设计结构

    公开(公告)号：US07849433B2

    公开(公告)日：2010-12-07

    申请号：US12117771

    申请日：2008-05-09

    申请人： Laura S. Chadwick ,  James A. Culp ,  David J Hathaway ,  Anthony D. Polson

    发明人： Laura S. Chadwick ,  James A. Culp ,  David J Hathaway ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0207 ,  G06F17/5072

    摘要： Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.

    摘要翻译： 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。

    FAST AND ACCURATE METHOD TO SIMULATE INTERMEDIATE RANGE FLARE EFFECTS
    8.
    发明申请
    FAST AND ACCURATE METHOD TO SIMULATE INTERMEDIATE RANGE FLARE EFFECTS 有权
    快速和准确的方法来模拟中间范围的瓦斯效应

    公开(公告)号：US20100175043A1

    公开(公告)日：2010-07-08

    申请号：US12349108

    申请日：2009-01-06

    申请人： Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield ,  Kafai Lai ,  Alan E. Rosenbluth

    发明人： Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield ,  Kafai Lai ,  Alan E. Rosenbluth

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36 ,  G03F1/70

    摘要： A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5λ/NA to distance ROI2 when the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROI1 to ROI2 are smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy.

    摘要翻译： 提供了一种用于在用于制造半导体集成电路的光掩模的设计中对光刻工艺进行建模的方法，更具体地说，用于模拟中间范围闪光效应。 对于当点扩散函数具有根据预定标准缓慢变化的斜率时，从约5λ/ NA的第一ROI1到距离ROI2的影响区域（ROI），则至少在从ROI1到ROI2的距离范围内的掩模形状 在计算SOCS卷积之前进行平滑处理。 该方法提供了一种用于以足够的精度模拟中等范围闪光效果的快速方法。

    METHODOLOGY TO IMPROVE TURNAROUND FOR INTEGRATED CIRCUIT DESIGN
    9.
    发明申请
    METHODOLOGY TO IMPROVE TURNAROUND FOR INTEGRATED CIRCUIT DESIGN 失效
    改进集成电路设计的方法

    公开(公告)号：US20080282211A1

    公开(公告)日：2008-11-13

    申请号：US11747485

    申请日：2007-05-11

    申请人： James A. Culp ,  Maharaj Mukherjee ,  Timothy G. Dunham ,  Mark Lavin

    发明人： James A. Culp ,  Maharaj Mukherjee ,  Timothy G. Dunham ,  Mark Lavin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.

    摘要翻译： 提供了一种设计用于制造集成电路的布局的方法，其中，通过设计处理的计算密集部分（诸如通过掩模设计传送的图像的模拟）或电路的电特性的模拟被更高效地执行 仅在具有相同几何上下文的计算子单元的单个实例上执行这样的计算。 因此，不是基于功能布局执行这样的计算，而是通过典型的设计过程步骤导致功能层次结构的显着平坦化，从而增加计算成本，本发明对基于几何的层次结构存储的计算子单元进行模拟 上下文，最大限度地降低了模拟成本。 随后根据功能布局组合得到的模拟结果。

    Halo-free non-rectifying contact on chip with halo source/drain diffusion
    10.
    发明授权
    Halo-free non-rectifying contact on chip with halo source/drain diffusion 有权
    光环/漏极扩散芯片上的无光非整流接触

    公开(公告)号：US06429482B1

    公开(公告)日：2002-08-06

    申请号：US09589719

    申请日：2000-06-08

    申请人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

    发明人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

    IPC分类号： H01L2976

    CPC分类号： H01L29/4966 ,  H01L29/1083 ,  H01L29/7835

    摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

    摘要翻译： 半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。 卤素扩散与整流接触扩散相邻，并且没有卤素扩散与非整流接触扩散相邻。整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。 非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。 避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。 在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。