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    METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT
    2.
    发明申请
    METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT 失效
    通过调节选择性电压激活切割点来优化功率的方法

    公开(公告)号：US20090228843A1

    公开(公告)日：2009-09-10

    申请号：US12041729

    申请日：2008-03-04

    申请人： Theodoros E. Anemikos ,  Jeanne Bickford ,  Laura S. Chadwick ,  Susan K. Lichtensteiger ,  Anthony D. Polson

    发明人： Theodoros E. Anemikos ,  Jeanne Bickford ,  Laura S. Chadwick ,  Susan K. Lichtensteiger ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.

    摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路和相对较快的集成电路器件。 该方法选择初始操作速度切割点以使相对较慢的集成电路和相对快速的集成电路器件的最大功率电平最小化。 然后，该方法使用集成电路设计制造集成电路器件，并测试集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始切割点调整到最终切割点，以使相对较慢的集成电路和相对较快的集成电路器件的最大功率电平最小化。

    Method of generating wiring routes with matching delay in the presence of process variation
    3.
    发明授权
    Method of generating wiring routes with matching delay in the presence of process variation 有权
    在存在过程变化的情况下生成具有匹配延迟的布线路线的方法

    公开(公告)号：US07418689B2

    公开(公告)日：2008-08-26

    申请号：US10908102

    申请日：2005-04-27

    申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

    摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

    Method of generating wiring routes with matching delay in the presence of process variation
    5.
    发明授权
    Method of generating wiring routes with matching delay in the presence of process variation 有权
    在存在过程变化的情况下生成具有匹配延迟的布线路线的方法

    公开(公告)号：US07823115B2

    公开(公告)日：2010-10-26

    申请号：US12108629

    申请日：2008-04-24

    申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

    摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

    Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point
    6.
    发明授权
    Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point 失效
    通过调整选择性电压分档切割点来优化集成电路设计的功耗的方法

    公开(公告)号：US07810054B2

    公开(公告)日：2010-10-05

    申请号：US12041729

    申请日：2008-03-04

    申请人： Theodoros E. Anemikos ,  Jeanne Bickford ,  Laura S. Chadwick ,  Susan K. Lichtensteiger ,  Anthony D. Polson

    发明人： Theodoros E. Anemikos ,  Jeanne Bickford ,  Laura S. Chadwick ,  Susan K. Lichtensteiger ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast identically designed integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests operating speeds and power consumption levels of the identically designed integrated circuit devices. Then, the method adjusts the initial operating speed cut point to a final operating speed cut point based on the testing, to minimize the maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast integrated circuit devices.

    摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路器件和相对较快的集成电路器件。 该方法选择初始操作速度切换点以使相对较慢的集成电路器件和相对快速的相同设计的集成电路器件的最大功耗水平最小化。 该方法然后使用集成电路设计制造集成电路器件，并测试相同设计的集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始操作速度切换点调整到最终操作速度切割点，以使相对较慢的集成电路器件和相对快速的集成电路器件的最大功耗水平最小化。

    System and method of analyzing timing effects of spatial distribution in circuits
    7.
    发明授权
    System and method of analyzing timing effects of spatial distribution in circuits 失效
    分析电路中空间分布的时序效应的系统和方法

    公开(公告)号：US07680626B2

    公开(公告)日：2010-03-16

    申请号：US11754625

    申请日：2007-05-29

    申请人： David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    发明人： David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    IPC分类号： G06F11/30 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.

    摘要翻译： 提供了系统和方法，用于通过考虑电路的路径或逻辑锥中的单元或元件的位置来分析电路的定时，包括集成电路。 在一个实施例中，可以围绕感兴趣的细胞或元件限定边界区域，并且可以使用边界区域的大小来计算定时松弛变化因子。 可以调整边界区域的大小以考虑定时延迟的变化。 在其他实施例中，可以使用路径或锥体内的元件或单元的位置或延迟加权位置以及用于计算定时松弛变化因子的质心来计算质心。 定时松弛变化因子用于计算电路的路径或逻辑锥的新的定时松弛。

    METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYSILICON PERIMETER DENSITIES OF INDIVIDUAL CELLS
    8.
    发明申请
    METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYSILICON PERIMETER DENSITIES OF INDIVIDUAL CELLS 有权
    基于个体电池的已知多晶硅密度的集成电路设计方法

    公开(公告)号：US20090282380A1

    公开(公告)日：2009-11-12

    申请号：US12117761

    申请日：2008-05-09

    申请人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    发明人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

    摘要翻译： 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

    IC CHIP DESIGN MODELING USING PERIMETER DENSITY TO ELECTRICAL CHARACTERISTIC CORRELATION
    9.
    发明申请
    IC CHIP DESIGN MODELING USING PERIMETER DENSITY TO ELECTRICAL CHARACTERISTIC CORRELATION 失效
    使用周密密度进行电子特性关联的IC芯片设计建模

    公开(公告)号：US20090210834A1

    公开(公告)日：2009-08-20

    申请号：US12031734

    申请日：2008-02-15

    申请人： Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

    发明人： Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

    IPC分类号： G06F9/45

    CPC分类号： G06F17/5081

    摘要： IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.

    摘要翻译： 公开了使用周界密度到电特性相关性的IC芯片设计建模。 在一个实施例中，一种方法可以包括确定集成电路（IC）芯片设计的多个区域的每个区域内的导电结构的周边密度; 将基于IC芯片设计的IC芯片的相应区域中的测量电特性与周围密度相关联; 并根据相关性对IC芯片设计进行建模。

    Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit
    10.
    发明申请
    Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit 审中-公开
    具有省电输入输出电路的集成电路的设计结构和测试这种集成电路的方法

    公开(公告)号：US20090115447A1

    公开(公告)日：2009-05-07

    申请号：US11933646

    申请日：2007-11-01

    申请人： Theodoros E. Anemikos ,  Michael R. Ouellette ,  Anthony D. Polson

    发明人： Theodoros E. Anemikos ,  Michael R. Ouellette ,  Anthony D. Polson

    IPC分类号： H03K19/003

    CPC分类号： G06F17/505 ,  G01R31/3016 ,  G01R33/072 ,  G06F2217/14

    摘要： A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the internal digital, analog, or mixed-signal circuitry of the integrated circuit. The transparent latches are transitioned between a pass-through mode and a state-saving mode via a common control signal. In anticipation of, for example, a predicted I/O signal disturbance generating event, the transparent latches are set to the state-saving mode. Consequently, the outputs of the transparent latches are held stable and glitchless during the disturbance event, which ensures that the internal logic of the integrated circuit does not lose state.

    摘要翻译： 一种用于集成电路的设计结构，其包括能够在任何预测的I / O干扰事件期间稳定I / O状态的输入/输出（I / O）状态保存电路。 I / O状态保存电路包括布置在多个相应I / O接收器的输出端与集成电路的内部数字，模拟或混合信号电路之间的多个透明锁存器。 透明锁存器通过公共控制信号在通过模式和状态保存模式之间转换。 在预期的例如预测的I / O信号干扰发生事件中，透明锁存器被设置为状态保存模式。 因此，在干扰事件期间，透明锁存器的输出保持稳定和无毛刺，这确保了集成电路的内部逻辑不会失去状态。