公开(公告)号：US08791562B2

公开(公告)日：2014-07-29

申请号：US13183645

申请日：2011-07-15

Applicant: Chung-sun Lee ,  Jung-Hwan Kim ,  Yun-hyeok Im ,  Ji-hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-kyoung Choi ,  Tae-hong Min

Inventor： Chung-sun Lee ,  Jung-Hwan Kim ,  Yun-hyeok Im ,  Ji-hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-kyoung Choi ,  Tae-hong Min

IPC: H01L23/58 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Abstract translation: 可用于三维（3D）系统级封装（SIP））的堆叠封装包括第一半导体芯片，第二半导体芯片和支持器。 第一半导体芯片包括贯通硅通孔（TSV），第二半导体芯片堆叠在第一半导体芯片上，并通过第一半导体芯片的TSV与第一半导体芯片电连接。 支撑件附接到第一半导体芯片上，以便与第二半导体芯片的边缘间隔开。

公开(公告)号：US08604614B2

公开(公告)日：2013-12-10

申请号：US13073250

申请日：2011-03-28

Applicant: Heung-kyu Kwon ,  Seok-won Lee ,  Hyon-chol Kim ,  Su-chang Lee ,  Chi-young Lee

Inventor： Heung-kyu Kwon ,  Seok-won Lee ,  Hyon-chol Kim ,  Su-chang Lee ,  Chi-young Lee

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/17 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/00 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

公开(公告)号：US20120018871A1

公开(公告)日：2012-01-26

申请号：US13183645

申请日：2011-07-15

Applicant: Chung-sun LEE ,  Jung-Hwan Kim ,  Yun-Hyeok Im ,  Ji-Hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-Kyong Choi ,  Tae-hong Min

Inventor： Chung-sun LEE ,  Jung-Hwan Kim ,  Yun-Hyeok Im ,  Ji-Hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-Kyong Choi ,  Tae-hong Min

IPC: H01L23/58

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Abstract translation: 可用于三维（3D）系统级封装（SIP））的堆叠封装包括第一半导体芯片，第二半导体芯片和支持器。 第一半导体芯片包括贯通硅通孔（TSV），第二半导体芯片堆叠在第一半导体芯片上，并通过第一半导体芯片的TSV与第一半导体芯片电连接。 支撑件附接到第一半导体芯片上，以便与第二半导体芯片的边缘间隔开。

公开(公告)号：US20170154878A1

公开(公告)日：2017-06-01

申请号：US15342689

申请日：2016-11-03

Applicant: Jae-Choon Kim ,  Eon-Soo Jang ,  Eun-Hee Jung ,  Hyon-Chol Kim ,  Byeong-Yeon Cho

Inventor： Jae-Choon Kim ,  Eon-Soo Jang ,  Eun-Hee Jung ,  Hyon-Chol Kim ,  Byeong-Yeon Cho

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00

Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

公开(公告)号：US20120280404A1

公开(公告)日：2012-11-08

申请号：US13459843

申请日：2012-04-30

Applicant: Heung-Kyu Kwon ,  Jae-Wook Yoo ,  Hyon-Chol Kim ,  Su-Chang Lee ,  Min-Ok Na

Inventor： Heung-Kyu Kwon ,  Jae-Wook Yoo ,  Hyon-Chol Kim ,  Su-Chang Lee ,  Min-Ok Na

IPC: H01L23/52

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16221 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83097 ,  H01L2224/83191 ,  H01L2225/06503 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.

Abstract translation: 堆叠封装包括下封装，其包括下封装基板和设置在下封装基板上的下半导体芯片，上封装，包括上封装基板和布置在上封装基板上的上半导体芯片，形成在下封装基板上的紧固元件 下部半导体芯片的上表面和上部封装基板的底面，以及将下部封装基板连接到上部封装基板的无卤素的封装间连接器。

公开(公告)号：US20110233771A1

公开(公告)日：2011-09-29

申请号：US13073250

申请日：2011-03-28

Applicant: Heung-kyu Kwon ,  Seok-won Lee ,  Hyon-chol Kim ,  Su-chang Lee ,  Chi-young Lee

Inventor： Heung-kyu Kwon ,  Seok-won Lee ,  Hyon-chol Kim ,  Su-chang Lee ,  Chi-young Lee

IPC: H01L23/488

CPC classification number: H01L24/17 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/00 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract translation: 半导体封装可以包括具有第一表面和第二表面的衬底本体。 半导体芯片可以安装在第一表面上，并且多个电极焊盘可以在第二表面上并且选择性地形成为具有从基板主体的中心区域朝向基板主体的外边缘延伸的逐渐变小或更大的尺寸 在半导体封装的回流焊工艺翘曲曲线上。