公开(公告)号：US5295090A

公开(公告)日：1994-03-15

申请号：US66674

申请日：1993-05-24

申请人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

发明人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

IPC分类号： G06F7/50 ,  G06F7/506

CPC分类号： G06F7/506

摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。

公开(公告)号：US4835418A

公开(公告)日：1989-05-30

申请号：US121542

申请日：1987-11-17

申请人： Hung-Cheng Hsieh

发明人： Hung-Cheng Hsieh

IPC分类号： H03K5/02 ,  H03K19/094

CPC分类号： H03K5/026 ,  H03K19/09429

摘要： A bidirectional buffer having a high impedance state is provided. This buffer is used for amplifying a signal as it is passed from one transmission line to another when it is desirable to select which direction the signal will flow. A switching circuit controls which transmission line is connected to the input terminal of the buffer and which is connected to the output terminal. A high impedance state is also provided for disconnecting the two transmission lines. Two memory cells control the direction of signal flow and the high impedance state.

摘要翻译： 提供具有高阻抗状态的双向缓冲器。 当希望选择信号将流向哪个方向时，该缓冲器用于将信号从一条传输线路传递到另一条传输线路时放大信号。 开关电路控制哪个传输线连接到缓冲器的输入端并连接到输出端。 还提供了用于断开两条传输线路的高阻抗状态。 两个存储单元控制信号流动的方向和高阻抗状态。

公开(公告)号：US5432719A

公开(公告)日：1995-07-11

申请号：US284935

申请日：1994-08-01

申请人： Ross H. Freeman ,  Hung-Cheng Hsieh

发明人： Ross H. Freeman ,  Hung-Cheng Hsieh

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K19/003

CPC分类号： H03K19/1736

摘要： This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

摘要翻译： 本发明提供了具有逻辑功能的可配置逻辑阵列的附加电路，逻辑功能通过加载存储器单元来编程，这导致逻辑阵列产生期望的功能。 使用附加电路，存储器单元也可以用作在操作期间由逻辑阵列的其他部分访问的存储器。

公开(公告)号：USRE34808E

公开(公告)日：1994-12-20

申请号：US610603

申请日：1990-11-08

申请人： Hung-Cheng Hsieh

发明人： Hung-Cheng Hsieh

IPC分类号： H03K3/353 ,  H03K3/3565 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K3/356 ,  H03K19/0175

CPC分类号： H03K3/3565 ,  H03K19/00361 ,  H03K19/018521

摘要： A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the Schmitt trigger. The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.

摘要翻译： TTL / CMOS兼容输入缓冲电路包括施密特触发器输入缓冲级和参考电压发生器。 在TTL模式中，参考电压发生器提供具有将施密特触发器的触发点强制到预定值的电平的参考电压。 在CMOS模式下，参考电压发生器被禁止，而施密特触发器提供等于电源电压的电压。 输入缓冲电路提供增强的输入噪声容限，并最大限度降低直流功率损耗。

公开(公告)号：US5148390A

公开(公告)日：1992-09-15

申请号：US707264

申请日：1991-05-24

申请人： Hung-Cheng Hsieh

发明人： Hung-Cheng Hsieh

IPC分类号： G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412

CPC分类号： G11C7/12 ,  G11C11/41 ,  G11C11/412 ,  G11C7/20 ,  G11C8/08

摘要： A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

摘要翻译： 可以从单个数据线可靠地读取和写入的五晶体管存储单元。 电池包括两个反相器和一个传输晶体管。 单元读/写电路包括地址供应电压源，其在写入期间保持在第一电平，并且在读取期间保持在第二电平，被选择以减少读取干扰。 存储单元读取电路包括用于在读取之前对单元数据线进行预充电的电路。 即使在读取操作期间，存储单元的状态在输出节点处连续可用以控制其它电路。 存储器单元中的反相器的上拉晶体管的选择性掺杂在存储单元被加电之后控制存储单元的初始状态。

公开(公告)号：US4902910A

公开(公告)日：1990-02-20

申请号：US121962

申请日：1987-11-17

申请人： Hung-Cheng Hsieh

发明人： Hung-Cheng Hsieh

IPC分类号： G01R31/319 ,  G01R19/165 ,  H03K17/22 ,  H03K17/30

CPC分类号： H03K17/223 ,  H03K17/302

摘要： A power supply voltage level sensing circuit on an integrated circuit generates a reset signal that holds the components of the integrated circuit in a defined state when the power supply voltage level drops below a predetermined voltage. The reset signal is released when the power supply voltage level returns to above the predetermined voltage.The voltage level sensing circuit is comprised of two inverters and a filter circuit. The inverters start to conduct at different power supply voltage levels and have different trigger point characteristics.The power supply voltage level sensing circuit may be coupled with a power-on reset circuit to create a voltage sensing power-on reset circuit which generates a reset signal not only when the power supply voltage is first supplied to the circuit, but also when the power supply voltage level temporarily falls below a selected value.

摘要翻译： 当电源电压电平降低到预定电压以下时，集成电路上的电源电压电平检测电路产生将集成电路的组件保持在限定状态的复位信号。 当电源电压电平恢复到预定电压以上时，复位信号被释放。 电压电平检测电路由两个反相器和一个滤波电路构成。 逆变器开始在不同的电源电压电平下进行，具有不同的触发点特性。 电源电压电平检测电路可以与上电复位电路耦合，以产生电压感测上电复位电路，其不仅在电源电压首先被提供给电路时，而且当电源电压电平检测电路 电源电压电平暂时低于选定值。

公开(公告)号：US4821233A

公开(公告)日：1989-04-11

申请号：US201509

申请日：1988-06-02

申请人： Hung-Cheng Hsieh

发明人： Hung-Cheng Hsieh

IPC分类号： G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/41 ,  G11C11/412 ,  G11C7/12 ,  G11C7/20 ,  G11C8/08

摘要： A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

摘要翻译： 可以从单个数据线可靠地读取和写入的五晶体管存储单元。 电池包括两个反相器和一个传输晶体管。 单元读/写电路包括地址供应电压源，其在写入期间保持在第一电平，并且在读取期间保持在第二电平，被选择以减少读取干扰。 存储单元读取电路包括用于在读取之前对单元数据线进行预充电的电路。 即使在读取操作期间，存储单元的状态在输出节点处连续可用以控制其它电路。 存储器单元中的反相器的上拉晶体管的选择性掺杂在存储单元被加电之后控制存储单元的初始状态。

公开(公告)号：US5267187A

公开(公告)日：1993-11-30

申请号：US944002

申请日：1992-09-11

申请人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

发明人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

IPC分类号： G06F7/50 ,  G06F7/57

CPC分类号： G06F7/57 ,  G06F7/503 ,  G06F7/5057 ,  G06F7/506

摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。

公开(公告)号：US4855619A

公开(公告)日：1989-08-08

申请号：US121963

申请日：1987-11-17

申请人： Hung-Cheng Hsieh ,  William S. Carter

发明人： Hung-Cheng Hsieh ,  William S. Carter

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/177

CPC分类号： H03K19/00361 ,  H03K19/018557 ,  H03K19/17712

摘要： A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.

摘要翻译： 作为可配置逻辑阵列的一部分的可编程连接传输线的可编程互连与在逻辑阵列内的逻辑阵列中的缓冲器组合，其中信号将从低电容线行进到较高电容线。 在这种布置中使用缓冲器允许控制逻辑阵列的配置的可编程互连更小; 消耗较少的功率，并且即使在通过长串可编程互连传播时也能提供更快的输出信号上升和下降。 教导了可编程控制互连的几种布置。 还教导了实现非常宽的AND门的手段，而不需要级联较小的器件。

公开(公告)号：US4820937A

公开(公告)日：1989-04-11

申请号：US778344

申请日：1985-09-19

申请人： Hung-Cheng Hsieh

发明人： Hung-Cheng Hsieh

IPC分类号： H03K3/3565 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/094 ,  H03K19/092

CPC分类号： H03K19/0948 ,  H03K19/018521 ,  H03K3/3565

摘要： A TTL/CMOS compatible input buffer includes an input inverter and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage to the source of the P-channel transistor in the inverter having a magnitude which forces the trigger point of the input inverter to assume a preselected value. Typically the preselected value is selected to be 1.4 volts in order to maximize the input noise margins. A second stage input inverter introduces hysteresis to improve the noise immunity of the system. The reference voltage generator includes an operational amplifier connected to a voltage divider network. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to power supply voltage is provided to the input inverter. As a result, the trigger point of input inverter is higher than 1.4 volts which provides a larger input noise margin. The voltage divider network and the operational amplifier are powered down so that no DC power is consumed.

摘要翻译： TTL / CMOS兼容输入缓冲器包括输入反相器和参考电压发生器。 在TTL模式中，参考电压发生器向逆变器中的P沟道晶体管的源极提供参考电压，其具有强制输入反相器的触发点呈现预选值的幅度。 通常，预选值被选择为1.4伏，以便最大化输入噪声容限。 第二级输入反相器引入滞后，以提高系统的抗噪声能力。 参考电压发生器包括连接到分压器网络的运算放大器。 在CMOS模式下，参考电压发生器被禁止，并且与输入逆变器提供等于电源电压的电压。 结果，输入反相器的触发点高于1.4伏，这提供了更大的输入噪声容限。 分压器网络和运算放大器掉电，不会消耗直流电源。