公开(公告)号：US5412688A

公开(公告)日：1995-05-02

申请号：US199354

申请日：1994-02-18

Applicant: Roland Marbot

Inventor： Roland Marbot

IPC: H04L29/00 ,  H03K5/02 ,  H04B1/58 ,  H04L5/14 ,  H04L25/02 ,  H04L29/14 ,  H04L5/16 ,  H04L27/00

CPC classification number: H03K5/026 ,  H04B1/58 ,  H04L5/1423

Abstract: In certain bidirectional transmissions, differential links (L, L*) are used and transceivers (1) that furnish differential measurement signals (V, V*) representative of the transmission signals of the remote station are used. To reduce power consumption, the electrical power to the transceivers (1) may be interrupted during periods of inactivity. The method of the present invention consists in determining a threshold value which is intermediate in value between the maximum and minimum values that can be assumed by the measurement signals (V, V*), and furnishing a signal (VAL) representative of transmission activity resulting from the comparison between the measurement signals (V, V*) and the threshold value. The circuit for employing the method uses voltage comparators and may be an integrated circuit.

Abstract translation: 在某些双向传输中，使用差分链路（L，L *），并且使用提供表示远程站的传输信号的差分测量信号（V，V *）的收发器（1）。 为了降低功耗，收发器（1）的电力可能在不活动期间中断。 本发明的方法在于确定在测量信号（V，V *）可以假设的最大值和最小值之间的中间值的阈值，并提供表示传输活动的信号（VAL） 从测量信号（V，V *）和阈值之间的比较。 采用该方法的电路使用电压比较器，并且可以是集成电路。

公开(公告)号：US3643223A

公开(公告)日：1972-02-15

申请号：US3643223D

申请日：1970-04-30

Applicant: HONEYWELL INF SYSTEMS

Inventor： RUTH RICHARD L ,  SHELLY WILLIAM A

IPC: H03K5/02 ,  H03K19/018 ,  H04L5/16 ,  G06F13/00

CPC classification number: H03K19/01831 ,  H03K5/026 ,  H04L5/16

Abstract: A communicating port in an information processing device is equipped with an interconnected logic gating wherein the bidirectional transmission line is connected to an output of one logic gate and to an input of another logic gate. Series and parallel interconnections permit one bidirectional transmission line for each bit of information per device and per port of each device, respectively. A transmitter-receiver circuit pair is disclosed for the logic gating using current mode logic driving a grounded base amplifier.

Abstract translation: 信息处理装置中的通信端口配备有互连逻辑门控，其中双向传输线连接到一个逻辑门的输出和另一个逻辑门的输入。 串行和并行互连分别允许每个设备和每个设备的每个端口的每个位的信息的一个双向传输线。 公开了一种使用驱动接地基放大器的电流模式逻辑的逻辑门控的发射机 - 接收机电路对。

公开(公告)号：US5559456A

公开(公告)日：1996-09-24

申请号：US106551

申请日：1993-08-16

Applicant: Tsuguyasu Hatsuda

Inventor： Tsuguyasu Hatsuda

IPC: G11C7/06 ,  H03K5/02 ,  H03F3/45

CPC classification number: G11C7/067 ,  H03K5/026

Abstract: In the present invention, there are disposed (i) a P-channel MOSFET for detecting variations of the voltage level of a data line to supply an electric current, and (ii) a current mirror circuit to which an electric current from the P-channel MOSFET is entered as a reference current and of which output current terminal is connected to the data line. When the data line is lowered in voltage level so that an electric current flows from the P-channel MOSFET to the current mirror circuit, an output current of the current mirror circuit flows to the drain of an N-channel MOSFET, so that the data line is electrically discharged. Thus, there is achieved a sensing circuit unit which is suitably used for a dynamic circuit and which can detect, at a high speed, variations of the voltage level of the data line as precharged.

Abstract translation: 在本发明中，设置（i）用于检测数据线的电压电平的变化以提供电流的P沟道MOSFET，以及（ii）电流镜电路，其中来自P- 通道MOSFET作为参考电流输入，其输出电流端子连接到数据线。 当数据线在电压电平下降使得电流从P沟道MOSFET流到电流镜电路时，电流镜电路的输出电流流向N沟道MOSFET的漏极，使得数据线 线路电气放电。 因此，实现了适合用于动态电路的感测电路单元，并且可以高速检测预充电的数据线的电压电平的变化。

公开(公告)号：US5532630A

公开(公告)日：1996-07-02

申请号：US281509

申请日：1994-07-27

Applicant: Charles D. Waggoner ,  Richard J. Blumberg ,  Gary B. Kotzur

Inventor： Charles D. Waggoner ,  Richard J. Blumberg ,  Gary B. Kotzur

IPC: G06F3/00 ,  H03K3/356 ,  H03K5/02 ,  H03K19/0175 ,  H04L29/10 ,  H03K3/00 ,  H03K17/16

CPC classification number: H03K5/026 ,  H03K3/356104

Abstract: A bidirectional input/output buffer is disclosed, where the receiver includes complementary bus keeper transistors. The keeper transistors are of opposite conductivity types, and have their gates coupled to the output of a receiver inverter. The keeper transistors thus reinforce the driven data state at the input of the receiver, in CMOS latch fashion, and hold the prior data state thereon after the driving output driver is in tristate. The keeper transistors have significantly weaker drive characteristics than the other receiver transistors, and than typical output drivers, so that the keeper transistors can be easily overdriven with the next data state, if different. In addition, the source/drain resistance of the keeper transistors is also preferably quite high, so that the power dissipation on switching is relatively low. These characteristics are readily achievable by providing relatively long channel lengths for the keeper transistors, relative to other transistors in the circuit.

Abstract translation: 公开了一种双向输入/输出缓冲器，其中接收器包括互补的总线保持器晶体管。 保持器晶体管具有相反的导电类型，并且其栅极耦合到接收器反相器的输出。 保持器晶体管因此以CMOS锁存方式加强了接收器输入处的驱动数据状态，并且在驱动输出驱动器处于三态之后保持其先前的数据状态。 保持器晶体管的驱动特性明显弱于其他接收晶体管，而不是典型的输出驱动器，因此如果不同，保持晶体管可以容易地过渡到下一个数据状态。 此外，保持晶体管的源极/漏极电阻也优选相当高，使得开关时的功率耗散相对较低。 通过相对于电路中的其它晶体管为保持器晶体管提供相对长的沟道长度，可以容易地实现这些特性。

公开(公告)号：US5202593A

公开(公告)日：1993-04-13

申请号：US785299

申请日：1991-10-30

Applicant: Thomas B. Huang ,  Yih-Chyun Jenq ,  Keith Lofstrom

Inventor： Thomas B. Huang ,  Yih-Chyun Jenq ,  Keith Lofstrom

IPC: H03K19/0175 ,  H03K5/02 ,  H04L5/16

CPC classification number: H03K5/026

Abstract: A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.

Abstract translation: 双向总线中继器包括两个单向总线中继器，用于在两条总线之间的相反方向重新发送信号。 当外部总线驱动器将总线拉低时，其中一个单向总线中继器将另一个总线拉低。 当外部总线驱动器允许总线上升到高逻辑电平时，单向总线中继器临时向另一个总线提供高充电电流，以快速将其拉高。 每个单向总线中继器还产生指示何时正在向上或向下拉动其输出总线的信号，并且当另一个单向总线中继器正在主动驱动其输出时，指示信号禁止一个单向总线中继器主动驱动其输出。

公开(公告)号：US4945395A

公开(公告)日：1990-07-31

申请号：US449435

申请日：1989-12-11

Applicant: Yoshiyuki Suehiro

Inventor： Yoshiyuki Suehiro

IPC: H01L21/822 ,  H01L21/60 ,  H01L27/04 ,  H01L27/118 ,  H03K5/02 ,  H03K19/173

CPC classification number: H01L24/06 ,  H01L27/11898 ,  H03K19/1735 ,  H03K5/026 ,  H01L2224/05554 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011

Abstract: A semiconductor circuit comprises basic cells formed in an internal cell region on an integrated-circuit chip and pads for input/output cells, the pads being arranged in peripheral regions on said chip. The semiconductor circuit further comprises first logic circuit means provided for each of the input/output cells, each including logic circuits formed by transistors of relatively high drive capability which are a part of said respective input/output cells, the first logic circuit means being positioned in the perpheral regions. The present invention also comprises second logic circuit means provided for each of the input/output cells, each including remaining logic circuits of the respective input/output cells, the second logic circuit being formed by the basic cells formed in the internal cell regions, so that each of said input/output cells is formed by one pad and the combination of the first and second logic circuit means.

Abstract translation: 半导体电路包括形成在集成电路芯片上的内部单元区域中的基本单元和用于输入/输出单元的焊盘，所述焊盘布置在所述芯片上的外围区域中。 半导体电路还包括为每个输入/输出单元提供的第一逻辑电路装置，每个单元包括由作为所述相应输入/输出单元的一部分的较高驱动能力的晶体管形成的逻辑电路，第一逻辑电路装置被定位 在永久地区。 本发明还包括为每个输入/输出单元提供的第二逻辑电路装置，每个单元包括各个输入/输出单元的剩余逻辑电路，第二逻辑电路由形成在内部单元区域中的基本单元形成，因此 每个所述输入/输出单元由一个焊盘和第一和第二逻辑电路装置的组合形成。

公开(公告)号：US4835418A

公开(公告)日：1989-05-30

申请号：US121542

申请日：1987-11-17

Applicant: Hung-Cheng Hsieh

Inventor： Hung-Cheng Hsieh

IPC: H03K5/02 ,  H03K19/094

CPC classification number: H03K5/026 ,  H03K19/09429

Abstract: A bidirectional buffer having a high impedance state is provided. This buffer is used for amplifying a signal as it is passed from one transmission line to another when it is desirable to select which direction the signal will flow. A switching circuit controls which transmission line is connected to the input terminal of the buffer and which is connected to the output terminal. A high impedance state is also provided for disconnecting the two transmission lines. Two memory cells control the direction of signal flow and the high impedance state.

Abstract translation: 提供具有高阻抗状态的双向缓冲器。 当希望选择信号将流向哪个方向时，该缓冲器用于将信号从一条传输线路传递到另一条传输线路时放大信号。 开关电路控制哪个传输线连接到缓冲器的输入端并连接到输出端。 还提供了用于断开两条传输线路的高阻抗状态。 两个存储单元控制信号流动的方向和高阻抗状态。

公开(公告)号：US4982115A

公开(公告)日：1991-01-01

申请号：US305344

申请日：1989-02-02

Applicant: Waitak P. Lee

Inventor： Waitak P. Lee

IPC: H03K5/02

CPC classification number: H03K5/026

Abstract: A digital circuit includes two digital signal sources, each having an output terminal connected to corresponding bus portions. Logic connects the two bus portions for propagating a signal pulse on one of the bus portions onto the other of the bus portion, and produces a digital indication signal signifying which of the signal sources generated the signal pulse. The logic includes logic gates, each having a first input connected to its corresponding bus portion, an output terminal connected to the indicator output, and a second input terminal connected to the output terminal of the opposite logic gate. The output of each logic gate also controls the connection of the other bus portion to a voltage source to bring that bus portion to the active state in response to the other bus portion being rendered active by its associated signal source.

Abstract translation: 数字电路包括两个数字信号源，每个数字信号源具有连接到相应总线部分的输出端子。 逻辑连接两个总线部分，用于将一个总线部分上的信号脉冲传播到总线部分的另一个上，并产生表示产生信号脉冲的信号源中的哪一个的数字指示信号。 该逻辑包括逻辑门，每个逻辑门具有连接到其对应的总线部分的第一输入端，连接到指示器输出的输出端子以及连接到相对逻辑门的输出端子的第二输入端子。 每个逻辑门的输出还控制另一个总线部分与电压源的连接，以使得该总线部分响应于其它总线部分被其相关联的信号源激活而处于活动状态。

公开(公告)号：US4935734A

公开(公告)日：1990-06-19

申请号：US905777

申请日：1986-09-10

Applicant: Kenneth Austin

Inventor： Kenneth Austin

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K5/02 ,  H03K17/687 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17748 ,  G06F17/5027 ,  H03K17/687 ,  H03K19/1733 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1778 ,  H03K5/026

Abstract: Configurable semiconductor integrated circuits as-made each have a plurality of logic circuits formed at discrete sites. For each logic circuit, direct selectably conducting/non-conducting connection paths extend from its output to input of a first set of other logic circuits and to its inputs from outputs of a second set of other logic circuits. All of the sets for all of the logic circuits are each different. Other direct connection paths are selectably connectable to inputs and outputs of the logic circuits. Selection can be irreversible or reversible and involves coincident signal addressing of the sites and coded configuring of the paths at that site. Reversible selection can be via field effect transistors or bipolar transistors and can be at or near normal logic signal levels and speeds. Versatile configurable input/output arrangements are described also reconfigurable data processing systems using the reversible transistor provisions.

Abstract translation: 可配置的半导体集成电路每个都具有在离散位置处形成的多个逻辑电路。 对于每个逻辑电路，直接可选地导通/不导通的连接路径从其输出延伸到第一组其他逻辑电路的输入，并从第二组其他逻辑电路的输出延伸到其输入。 所有逻辑电路的所有集合各不相同。 其他直接连接路径可选择地连接到逻辑电路的输入和输出。 选择可以是不可逆的或可逆的，并且涉及站点的重合信号寻址和该站点路径的编码配置。 可逆选择可以通过场效应晶体管或双极晶体管，并且可以处于或接近正常的逻辑信号电平和速度。 还描述了可复用的可配置输入/输出布置，这些可配置的数据处理系统使用可逆晶体管。

公开(公告)号：US4868419A

公开(公告)日：1989-09-19

申请号：US905846

申请日：1986-09-10

Applicant: Kenneth Austin

Inventor： Kenneth Austin

IPC: G11C11/409 ,  G06F17/50 ,  G11C11/406 ,  H03K5/02 ,  H03K17/687 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1778 ,  G06F17/5027 ,  H03K17/687 ,  H03K19/1733 ,  H03K19/1736 ,  H03K19/17704 ,  H03K5/026

Abstract: A gated binary signal transmission circuit in a field effect semiconductor chip comprises a single signal-pass transistor connected between a bit signal input to one of its electrodes and a bit signal output from another of its electrodes. Its control electrode is connected for temporary energizations by switching circuitry operative only at prescribed intervals, the single signal-pass transistor being operative to pass signals between such energizations of its control electrode. Conduction of the single-pass transistor between energizations will persist, though with some decay, due to inherent capacitance and the control electrode being left "floating" between energizations.

Abstract translation: 场效应半导体芯片中的门控二进制信号传输电路包括连接在输入到其电极之一的位信号和从另一个电极输出的位信号之间的单个信号传输晶体管。 其控制电极通过仅以规定间隔工作的开关电路连接用于临时通电，单个信号传输晶体管可操作以在其控制电极的这种通电之间传递信号。 在通电之间，单通晶体管的导通将持续，尽管由于固有电容而导致一些衰减，并且控制电极在通电之间“浮动”。