-
公开(公告)号：US5267187A
公开(公告)日：1993-11-30
申请号：US944002
申请日：1992-09-11
CPC分类号： G06F7/57 , G06F7/503 , G06F7/5057 , G06F7/506
摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.
摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。
-
公开(公告)号：US5295090A
公开(公告)日：1994-03-15
申请号：US66674
申请日：1993-05-24
CPC分类号： G06F7/506
摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.
摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。
-
搜索结果
2 条记录 (耗时 0.012 秒)
