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1.发明授权Quad-array diode-less RF-to-DC rectifying charge-pump converter for energy harvesting 有权用于能量收集的四阵列无二极管RF-DC整流电荷泵转换器公开(公告)号：US09385625B1
公开(公告)日：2016-07-05
申请号：US14686923
申请日：2015-04-15
摘要： A RF-to-DC converter charges a battery or powers a circuit from the energy of received radio waves. The RF energy received is very small for far-field applications, so the converter is highly sensitive. Four capacitor arrays are arranged in two banks. Buffered RF signals pump bottom plates of the capacitors. A series of L-switches in each bank connect between the two capacitor arrays in that bank. Each L switch has a pre-charge switch that charges that stage's input capacitor, and a stage-transfer switch that shares charge from the input capacitor to an output capacitor for that stage. Switches in the two banks alternately pre-charge and pump, with the left bank pumping while the right bank pre-charges. Switches are transistors with substrates tied to their sources or actively driven by substrate control signals. One bank may use n-channel transistors with the other bank uses p-channel transistors. Gate voltages may be boosted.
摘要翻译： RF-DC转换器对电池充电或从接收到的无线电波的能量为电路供电。 接收的RF能量对于远场应用来说非常小，因此转换器是高度敏感的。 四个电容器阵列布置在两个组中。 缓冲RF信号泵电容器的底板。 每个组中的一系列L开关连接在该组中的两个电容器阵列之间。 每个L开关具有对该级输入电容器进行充电的预充电开关，以及从该输入电容器向该级输出电容器共享电荷的级转换开关。 两岸交换机交替预充和泵，左岸泵送，右岸预充电。 开关是具有与其源极连接的基板或由基板控制信号主动驱动的晶体管。 一个bank可以使用n沟道晶体管，另一个bank可以使用p沟道晶体管。 栅极电压可能会升高。
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2.发明申请Digitally-Programmable Gain Amplifier with Direct-Charge Transfer and Offset Cancellation 有权具有直接电荷转移和偏移消除的数字可编程增益放大器公开(公告)号：US20150311868A1
公开(公告)日：2015-10-29
申请号：US14264252
申请日：2014-04-29
CPC分类号： H03F1/0233 , H03F1/0266 , H03F3/005 , H03F3/38 , H03F3/45071 , H03F3/45475 , H03F3/45605 , H03F2200/249 , H03F2200/405 , H03F2200/411 , H03F2200/471 , H03F2203/45116 , H03F2203/45512 , H03F2203/45536 , H03F2203/45544 , H03F2203/45616 , H03G1/0094 , H03G3/001 , H03G3/002
摘要： A Programmable-Gain Amplifier (PGA) has a digital value that programmably adjusts the gain of the analog amplifier. A variable capacitor has several switched sub-capacitors that are enabled by the digital value. Enabled sub-capacitors are switched between a sampled input and a virtual ground on one terminal, and connect to a summing node on the other terminal. The summing node connects to the inverting input of an op amp either through a switch or through a double-sampling capacitor that stores an offset. A feedback capacitor is in parallel with a sampling capacitor during a second clock phase when direct-charge transfer occurs, reducing power consumption of the amplifier. The feedback capacitor samples the sampled input during the first clock phase. The PGA gain is proportional to the sum of capacitances of enabled sub-capacitors. The gain can be adjusted for sensor inputs to an Analog Front-End (AFE), such as for an electro-cardiogram (ECG).
摘要翻译： 可编程增益放大器（PGA）具有可编程调节模拟放大器增益的数字值。 可变电容器具有通过数字值使能的几个开关子电容器。 启用子电容器在一个终端上的采样输入和虚拟地之间切换，并连接到另一个终端上的求和节点。 求和节点通过开关或通过存储偏移的双采样电容连接到运算放大器的反相输入。 当直接电荷转移发生时，反馈电容器在第二个时钟相位期间与采样电容并联，从而降低放大器的功耗。 反馈电容在第一个时钟阶段对采样输入进行采样。 PGA增益与使能子电容的电容之和成正比。 可以调整模拟前端（AFE）的传感器输入的增益，例如电心电图（ECG）。
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3.发明授权Electro-static-discharge (ESD) protection structure with stacked implant junction transistor and parallel resistor and diode paths to lower trigger voltage and raise holding volatge 有权具有堆叠式注入结晶体管和并联电阻器和二极管路径的静电放电（ESD）保护结构，以降低触发电压并提高保持电压公开(公告)号：US09054521B2
公开(公告)日：2015-06-09
申请号：US13925956
申请日：2013-06-25
发明人： Xiao Huo , Beiping Yan , Xiaowu Cai
CPC分类号： H02H9/046 , H01L27/0248 , H01L27/0259
摘要： An electro-static-discharge (ESD) protection circuit has a vertical NPN transistor with a floating p-type base created by a deep p-type implant under an N+ source region. The deep p-type implant may be an ESD implant in a standard CMOS process. The p-type implant provides a low initial snap-back trigger voltage, but the holding voltage may be too low, creating latch-up problems. The holding voltage is raised by about one volt by connecting the emitter of the vertical NPN transistor to parallel resistor and diode paths. When the vertical NPN transistor is triggered, its current initially flows through the resistor, creating an increasing voltage drop through the resistor as current rises. Once the voltage across the resistor reaches 0.5 volt, the diode in parallel with the resistor becomes forward biased and shunts a higher current than the resistor, raising the holding voltage. A clamp transistor may replace the diode.
摘要翻译： 静电放电（ESD）保护电路具有垂直NPN晶体管，其具有由N +源极区域下的深p型注入产生的浮动p型基极。 深p型植入物可以是标准CMOS工艺中的ESD注入。 p型注入提供了低的初始瞬态触发电压，但是保持电压可能太低，造成闩锁问题。 通过将垂直NPN晶体管的发射极连接到并联电阻和二极管路径，保持电压提高约一伏。 当垂直NPN晶体管被触发时，其电流最初流过电阻器，当电流上升时，通过电阻产生增加的电压降。 一旦电阻上的电压达到0.5伏特，与电阻并联的二极管就会正向偏置，并分流比电阻更高的电流，提高保持电压。 钳位晶体管可以替代二极管。
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4.发明申请公开(公告)号：US20170026723A1
公开(公告)日：2017-01-26
申请号：US14808030
申请日：2015-07-24
发明人： Ho Ming (Karen) WAN , Sze Wing LEUNG , Hok Mo YAU , Guang Jie CAI
CPC分类号： H04Q9/00 , H03M1/20 , H04B5/0056 , H04Q2209/40 , H04Q2209/886 , H04W4/70 , H04W4/80
摘要： A bio-sensing processor chip acts as an auto-configurable platform to support a wide variety of bio-sensors. Nano-wires with attached bio-receptors for specific bio-molecules, ECG, and SPO2 bio-sensors drive analog voltages or currents to analog inputs of the bio-sensing processor chip. These analog inputs are divided into three sections. An input sensor detector/decoder detects which analog inputs are active and configures an analog-to-digital converter (ADC) to convert first-section inputs to 12 digital bits, second-section inputs to 16 bits, and third-section inputs to 20 bits. An Analog Front-End (AFE) is bypassed for the first section inputs but amplifies and filters second and third section inputs. A Universal Asynchronous Receiver Transmitter (UART) sends the converted digital values to a nearby external device using NFC or WiFi transmitters. When no battery is detected, energy is harvested from NFC signals from the external device, and one-shot measurements are made.
摘要翻译： 生物传感处理器芯片充当自动配置平台，可支持各种生物传感器。 带有特定生物分子，ECG和SPO2生物传感器的附属生物受体的纳米线将模拟电压或电流驱动到生物传感处理器芯片的模拟输入。 这些模拟输入分为三个部分。 输入传感器检测器/解码器检测哪些模拟输入有效，并配置模数转换器（ADC），将第一部分输入转换为12位数字位，将第二段输入转换为16位，将第三段输入转换为20位 位。 对于第一部分输入，模拟前端（AFE）被旁路，但是对第二和第三部分输入进行放大和滤波。 通用异步收发器（UART）使用NFC或WiFi发送器将转换的数字值发送到附近的外部设备。 当没有检测到电池时，从外部设备的NFC信号中收集能量，并进行一次测量。
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5.发明授权LED driver with small output ripple without requiring a high-voltage primary-side electrolytic capacitor 有权LED驱动器具有输出纹波小，无需高压初级侧电解电容器公开(公告)号：US09306461B2
公开(公告)日：2016-04-05
申请号：US14315647
申请日：2014-06-26
发明人： Po Wah Chang , Chik Wai (David) Ng , Hing Kit Kwan , Wai Kit (Victor) So , Shaobin Wu , Kwok Kuen (David) Kwong
CPC分类号： H02M3/33507 , H02M1/15 , H02M1/42 , H02M1/4258 , H05B33/0815 , Y02B70/126
摘要： A power converter reduces output ripple without using an electrolytic primary-side capacitor that can reduce product lifetime. Primary-Side Regulation (PSR) using an auxiliary winding provides a regulated secondary voltage with some low-frequency ripple on a secondary winding of a transformer. A smaller secondary capacitor that is not an electrolytic capacitor filters the output of the secondary side. A bang-bang controller controls the secondary side current to reduce current ripple despite voltage ripple. The bang-bang controller has a series resistor and inductor in series with a load such as an LED. A voltage drop across the series resistor increases when a switch turns on. This increasing voltage drop toggles the switch off once an upper limit voltage is reached. The voltage drop then decreases as inductor current is shunted by a diode, until the voltage drop reaches a lower limit voltage and the switch toggles on again.
摘要翻译： 电源转换器可降低输出纹波，而不使用可减少产品寿命的电解初级侧电容器。 使用辅助绕组的初级侧调节（PSR）在变压器的次级绕组上提供具有一些低频纹波的稳定二次电压。 不是电解电容器的较小二次电容器对次级侧的输出进行滤波。 一个爆炸控制器控制二次侧电流，以减小电流纹波，尽管电压纹波。 爆轰控制器具有串联电阻和电感器，与负载如LED串联。 当开关导通时，串联电阻上的电压降会增加。 一旦达到上限电压，此增加的电压降切换开关。 随着电感电流由二极管分流，电压降降低，直到电压降达到下限电压，并且开关再次切换。
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6.发明申请Serial Multi-Battery Charger with Independent Simultaneous Charge and Discharge 有权具有独立同时充电和放电的串行多电池充电器公开(公告)号：US20150380959A1
公开(公告)日：2015-12-31
申请号：US14315611
申请日：2014-06-26
发明人： Po Wah CHANG , Chi Chiu TSANG , Chik Wai (David) NG , Yuanzhe XU , Wai Kei OR , Kwok Kuen (David) KWONG
IPC分类号： H02J7/00
CPC分类号： H02J7/0019 , H01M10/425 , H01M10/441 , H01M10/465 , H02J7/0016 , H02J7/0021 , H02J7/0026 , H02J7/0031 , H02J7/0045 , H02J7/0068 , Y02T90/124 , Y10T307/625 , Y10T307/653
摘要： A serial battery charger has a battery matrix with switches that are configured by a microcontroller that reads voltages between batteries to determine if each battery is fully-charged, charging, or absent. A switch configuration allows charging and discharging currents to flow simultaneously, and allows discharging current but blocks charging current from fully-charged batteries to prevent over-charging. The charging current flows through all charging batteries in series while the discharging current flows from all fully-charged and charging batteries in series. Blocking and bypass switches route the charging current to all charging batteries in series, but bypass all fully-charged and absent batteries. The blocking and bypass switches route the discharging current serially through all fully-charged and charging batteries in the battery matrix while avoiding absent batteries. The switches are controlled by the switch configuration from the microcontroller. Larger battery matrixes have row and column lines that are connected by connecting switches.
摘要翻译： 串行电池充电器具有电池矩阵，其中的开关由微控制器配置，用于读取电池之间的电压，以确定每个电池是否充满电，充电或不存在。 开关配置允许充电和放电电流同时流动，并允许放电电流，但阻止来自充满电的电池的充电电流以防止过充电。 充电电流串联流过所有充电电池，同时放电电流从所有充满电和充电电池串联流动。 阻塞和旁路开关将充电电流串联连接到所有充电电池，但绕过所有充满电和未充电的电池。 阻塞和旁路开关通过电池矩阵中的所有充满电和充电电池串联放电电流，同时避免电池不存在。 开关由微控制器的开关配置控制。 较大的电池矩阵具有通过连接开关连接的行和列线。
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7.发明授权Phase-to-amplitude converter for direct digital synthesizer (DDS) with reduced AND and reconstructed ADD logic arrays 有权具有降低的AND和重构ADD逻辑阵列的直接数字合成器（DDS）的相位到幅度转换器公开(公告)号：US09021002B2
公开(公告)日：2015-04-28
申请号：US13760012
申请日：2013-02-05
发明人： Zhongzi Chen , Beiping Yan , Xiao Huo , Xiaowu Cai
CPC分类号： G06F1/0321 , G06F1/0328 , G06F1/0353 , G06F1/0356
摘要： A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.
摘要翻译： 直接数字合成器（DDS）的正弦波发生器将数字相位输入转换为数字正弦波输出。 正弦值和斜率存储在只读存储器（ROM）中用于第一象限中的粗略高位相位。 象限文件夹和分相器反映和反转第一象限的值，以产生所有四个象限的幅度。 每个正弦值和斜率都存储在较低相位位的范围内。 一个Delta位分离高位和低位相位。 Delta有条件地反转低位相位，正弦值和最终极性。 减少的AND逻辑阵列将斜率乘以有条件反相的下相位位。 然后，重建的ADD逻辑阵列会添加有条件反转的正弦值。 添加有条件反转的极性以产生最终正弦值。 基于Delta位的条件反演精简生成逻辑。
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8.发明授权公开(公告)号：US08711982B1
公开(公告)日：2014-04-29
申请号：US13790951
申请日：2013-03-08
发明人： Guangjie Cai , Leung Ling (Alan) Pun , Tat Fu Chan
CPC分类号： H03D1/18
摘要： An envelope detector receives an input that is an Amplitude-Modulated (AM) or Amplitude-Shift-Keying (ASK) coded signal. Each channel has a sample switch and a diode that charge an internal sampling capacitor. A hold switch connects the internal sampling capacitor to a summing output capacitor or to a post-processing circuit. A reset switch discharges the internal sampling capacitor after each sample. Two or more channels may be time multiplexed to sample alternate cycles of the input, and then their outputs combined by the summing output capacitor or by the post-processing circuit. The diodes may be reversed to detect the negative envelope rather than the positive envelope. Clocks for the switches may be generated from the input, or may be from a separate clock source. Since the sampling window is open for a whole input cycle, the clock source is insensitive to phase error.
摘要翻译： 包络检测器接收作为幅度调制（AM）或幅移键控（ASK）编码信号的输入。 每个通道都有一个采样开关和一个对内部采样电容充电的二极管。 保持开关将内部采样电容器连接到求和输出电容器或后处理电路。 每个样品后，复位开关对内部采样电容放电。 两个或多个通道可以被时间复用以对输入的交替周期进行采样，然后它们的输出由加法输出电容器或后处理电路组合。 二极管可以反向以检测负信封而不是正信封。 用于开关的时钟可以从输入产生，或者可以来自单独的时钟源。 由于采样窗口为整个输入周期打开，因此时钟源对相位误差不敏感。
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公开(公告)号：US09661695B1
公开(公告)日：2017-05-23
申请号：US14939081
申请日：2015-11-12
发明人： Guangjie Cai , Ho Ming (Karen) Wan , Chun Fai Wong , Tai Yin Wong
IPC分类号： H03F3/04 , H03F3/30 , H05B33/08 , H03K17/687 , H03F3/45
CPC分类号： H05B33/0806 , H03F3/345 , H03F3/45179 , H03F2200/462 , H03F2200/471 , H03F2200/474 , H03F2200/91 , H03K17/6872 , H05B33/0827 , H05B33/0842
摘要： A low-headroom current driver does not use an op amp or resistor. A sensing transistor having its source connected to a drain of an output transistor senses variations in an output current. The gate, source, and drain voltages of the sensing transistor are mirrored to a sense mirror transistor to control a sense current. The sense current is mirrored to a reference source transistor to generate a mirrored sense current. An error between the mirrored sense current and a fixed reference current is stored as charge on an error-storing capacitor. The stored error charge creates a negative-feedback compensation current that adjusts a gate voltage generated by a feedback-driving transistor. The adjusted gate voltage controls the gate of the output transistor to compensate for the sensed variation in output current. The sensing current is also compensated using a sense-mirror tail transistor connected to the sense mirror transistor.
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公开(公告)号：US09640523B2
公开(公告)日：2017-05-02
申请号：US14847249
申请日：2015-09-08
发明人： Xiaowu Cai , Beiping Yan , Zhongzi Chen
IPC分类号： H01L27/02 , H01L29/74 , H01L29/749
CPC分类号： H01L27/0255 , H01L27/0262 , H01L29/7412 , H01L29/749
摘要： A lateral p-n diode in the center of and surrounded by a vertical Silicon-Controlled Rectifier (SCR) forms an Electro-Static-Discharge (ESD) protection structure. The lateral p-n diode has a cross-shaped P+ diode tap with four rectangles of N+ diode regions in each corner of the cross. A P-well under the P+ diode tap is also an anode of a vertical PNPN SCR that has a deep N-well in a P-substrate. The deep N-well surrounds the lateral diode. Triggering MOS transistors are formed just beyond the four ends of the cross shaped P+ diode tap. Each triggering MOS transistor has N+ regions at the edge of the deep N-well and in the P-substrate that act as the cathode terminals. A deep P+ implant region under the N+ region at the edge of the deep N-well decreases a trigger voltage of the vertical SCR.
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