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    Semiconductor memory device and method of producing the same
    1.
    发明授权
    Semiconductor memory device and method of producing the same 失效

    公开(公告)号：US06838333B2

    公开(公告)日：2005-01-04

    申请号：US10114989

    申请日：2002-04-04

    申请人： Hideki Takeuchi ,  Hirohiko Izumi

    发明人： Hideki Takeuchi ,  Hirohiko Izumi

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L21/76895

    摘要： A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

    Semiconductor memory device and method of producing the same
    3.
    发明授权
    Semiconductor memory device and method of producing the same 有权

    公开(公告)号：US07064029B2

    公开(公告)日：2006-06-20

    申请号：US11025903

    申请日：2005-01-03

    申请人： Hideki Takeuchi ,  Hirohiko Izumi

    发明人： Hideki Takeuchi ,  Hirohiko Izumi

    IPC分类号： H01L21/8238

    CPC分类号： H01L28/91 ,  H01L21/76895

    摘要： A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

    Semiconductor memory device and method of producing the same
    4.
    发明申请
    Semiconductor memory device and method of producing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20050145917A1

    公开(公告)日：2005-07-07

    申请号：US11025903

    申请日：2005-01-03

    申请人： Hideki Takeuchi ,  Hirohiko Izumi

    发明人： Hideki Takeuchi ,  Hirohiko Izumi

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/76

    CPC分类号： H01L28/91 ,  H01L21/76895

    摘要： A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

    摘要翻译： 半导体存储器件具有存取晶体管，其具有形成在半导体衬底上的栅极和一对杂质扩散层，以及具有存储节点电极和单元板电极的存储电容器。 电极通过由铁电体材料制成的电容绝缘层彼此连接。 存储节点电极具有被电容绝缘层覆盖的表面，并且在由覆盖存取晶体管的层间绝缘膜形成的孔中的一对杂质扩散层中的一个上形成为列的形状 一对杂质扩散层。 柱的上表面不超过层间绝缘膜。 形成在孔中的存储节点电极经由层间绝缘膜与电池板电极相对。

    Flattening method and apparatus for semiconductor device
    5.
    发明授权
    Flattening method and apparatus for semiconductor device 失效
    用于半导体器件的扁平化方法和装置

    公开(公告)号：US5877088A

    公开(公告)日：1999-03-02

    申请号：US745289

    申请日：1996-11-08

    申请人： Yamato Samitsu ,  Hirohiko Izumi

    发明人： Yamato Samitsu ,  Hirohiko Izumi

    IPC分类号： B24B49/16 ,  B24B37/013 ,  B24B49/04 ,  H01L21/304 ,  H01L21/66 ,  H01L21/00

    CPC分类号： B24B37/013 ,  B24B49/04 ,  H01L22/26 ,  H01L2924/0002

    摘要： When the surface of a semiconductor device having at least two different films formed on a substrate is flattened by chemical mechanical polishing, the abrasion resistance upon polishing is detected by strain gauges provided close to the surface of the semiconductor device to be polished. In addition, the end of the polishing process is determined on the basis of the amount of change of the detected signals produced from the strain gauges.

    摘要翻译： 当通过化学机械抛光将具有形成在基板上的至少两个不同膜的半导体器件的表面平坦化时，通过靠近待抛光的半导体器件的表面设置的应变计来检测抛光时的耐磨性。 此外，基于从应变计产生的检测信号的变化量来确定抛光处理的结束。

    Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof
    6.
    发明授权
    Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof 失效
    包括短路避免结构的半导体存储装置及其制造方法

    公开(公告)号：US06255686B1

    公开(公告)日：2001-07-03

    申请号：US09124852

    申请日：1998-07-30

    申请人： Hideki Takeuchi ,  Hirohiko Izumi

    发明人： Hideki Takeuchi ,  Hirohiko Izumi

    IPC分类号： H01L27108

    CPC分类号： H01L27/10855 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10885 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film. The lower electrode is filled inside the first and second contact holes to be formed in an island-like shape on the first insulating film through the protective film so as to be electrically connected with the one of the pair of impurity diffusion layers. Each of the first and second contact holes has a diameter which is made smaller by an existence of the second insulating film than a minimum dimension determined by an exposure limit in a photolithography.

    摘要翻译： 在半导体存储装置中，在由半导体衬底的器件隔离结构限定的器件激活区域处形成具有栅电极和一对杂质扩散层的存取晶体管。 在该存取晶体管的上方形成第一绝缘膜，该第一绝缘膜具有用于暴露该对杂质扩散层之一的表面的一部分的第一接触孔。 在第一绝缘膜上形成有形成在第一接触孔上的第二接触孔的保护膜。 第二绝缘膜形成在第一和第二接触孔的侧壁面上。 记忆电容器具有彼此相对并且通过电介质膜电容耦合的下部电极和上部电极。 下部电极填充在第一和第二接触孔的内部，以通过保护膜在第一绝缘膜上形成为岛状，以便与一对杂质扩散层电连接。 第一和第二接触孔中的每一个具有通过第二绝缘膜的存在使得比通过光刻中的曝光极限确定的最小尺寸更小的直径。

    Semiconductor memory device and method for fabricating the same
    7.
    发明授权
    Semiconductor memory device and method for fabricating the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US5644151A

    公开(公告)日：1997-07-01

    申请号：US453975

    申请日：1995-05-30

    申请人： Hirohiko Izumi ,  Shoichi Iwasa

    发明人： Hirohiko Izumi ,  Shoichi Iwasa

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A pair of electrically conductive regions of ruthenium dioxide are formed on a BPSG film covering DRAM memory cells arranged in a matrix form. The conductive region is extended in a column direction to be connected to one of impurity diffused regions of MOS transistors of the memory cells at contact holes, and also connected to one of impurity diffused regions of MOS transistors of column direction selection. Formed beneath the conductive region (capacitor upper electrodes) are capacitor lower electrodes connected to the other impurity diffused regions of the memory cell MOS transistors and a high-dielectric film. The conductive region is connected to a (1/2)Vcc power supply. Since the upper electrodes and wiring lines of capacitors can be formed at the same time, the number of steps in a fabrication method can be reduced.

    摘要翻译： 在覆盖以矩阵形式布置的DRAM存储单元的BPSG膜上形成一对二氧化钌导电区域。 导电区域在列方向上延伸以连接到接触孔处的存储单元的MOS晶体管的杂质扩散区域之一，并且还连接到列方向选择的MOS晶体管的杂质扩散区域之一。 形成在导电区域（电容器上电极）下方的是与存储单元MOS晶体管的其他杂质扩散区域连接的电容器下电极和高介电膜。 导电区域连接到（+ E，fra 1/2 + EE）Vcc电源。 由于可以同时形成电容器的上电极和布线，所以可以减少制造方法中的步数。

    Process for forming a thin metal film by chemical vapor deposition
    8.
    发明授权
    Process for forming a thin metal film by chemical vapor deposition 失效
    通过化学气相沉积法形成薄金属膜的工艺

    公开(公告)号：US5306666A

    公开(公告)日：1994-04-26

    申请号：US094226

    申请日：1993-07-21

    申请人： Hirohiko Izumi

    发明人： Hirohiko Izumi

    IPC分类号： H01L21/285 ,  H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/28556

    摘要： When a thin metal film is formed on a substrate at a constant substrate temperature by chemical vapor deposition while alternately and discontinuously introducing a raw material gas and a reducing gas onto the substrate, reducing the raw material gas with the reducing gas on the substrate, thereby conducting chemical vapor deposition, and repeating the chemical vapor deposition to obtain a desired film thickness, a thin metal film having a good surface flatness without any current leakage can be obtained without etching the substrate wafer, and when the reducing gas is excited to excited species by an exciting means at the introduction of the reducing gas and the excited species is used be reduce the raw material gas, a lower substrate temperature can be used and chemical vapor deposition process time can be made shorter than without using the exciting means.

    摘要翻译： 当通过化学气相沉积在基板上以恒定的基板温度形成薄金属薄膜，同时在基板上交替地且不连续地引入原料气体和还原气体时，用基板上的还原气体还原原料气体，由此 进行化学气相沉积，并重复化学气相沉积以获得所需的膜厚度，可以在不蚀刻基板晶片的情况下获得具有良好的表面平坦度而没有任何电流泄漏的薄金属膜，并且当还原气体被激发成激发态时 通过引进还原气体和激发物质的激励手段，可以减少原料气体，可以使用较低的基板温度，并且可以使化学气相沉积工艺的时间比不使用激发装置更短。

    Polishing abrasive grains, polishing agent and polishing method
    9.
    发明授权
    Polishing abrasive grains, polishing agent and polishing method 失效
    抛光磨粒，抛光剂和抛光方法

    公开(公告)号：US6022400A

    公开(公告)日：2000-02-08

    申请号：US81132

    申请日：1998-05-19

    申请人： Hirohiko Izumi ,  Masatoshi Sakai ,  Michihiro Yoshinaga

    发明人： Hirohiko Izumi ,  Masatoshi Sakai ,  Michihiro Yoshinaga

    IPC分类号： B24B53/007 ,  B24B53/017 ,  C09K3/14 ,  B24B1/00

    CPC分类号： B24B53/017 ,  C09K3/1436 ,  C09K3/1463

    摘要： Surfaces of substrates, typically semiconductor device substrates, are polished with a polishing agent comprising polishing abrasive grains of a metal oxide (e.g. cerium oxide, zirconium oxide or manganese oxide) having a hydrophilic surface and a surface potential (zeta potential) of not more than 50 mV at pH 7 in absolute value, preferably polishing abrasive grains having hydrophilic groups, preferably hydroxyl groups, at the extremities and then cleaned with an aqueous cleaning solution comprising pure water. The polishing abrasive grains remaining on the polished substrate surface can be removed to a satisfactory degree therefrom by simple cleaning using the aqueous cleaning solution only.

    摘要翻译： 衬底（通常为半导体器件衬底）的表面用抛光剂抛光，抛光剂包括抛光具有亲水表面和表面电位（ζ电位）不大于的金属氧化物（例如氧化铈，氧化锆或氧化锰）的磨料颗粒 优选在pH7下为绝对值为50mV，优选在末端抛光具有亲水基团，优选羟基的磨粒，然后用含有纯水的水性清洁溶液清洗。 通过使用仅含水清洗液的简单清洁，可以将残留在抛光的基材表面上的研磨磨粒除去至令人满意的程度。