公开(公告)号：US07903017B2

公开(公告)日：2011-03-08

申请号：US12549363

申请日：2009-08-28

申请人： Yi-Bin Hsieh ,  Heng-Chih Lin

发明人： Yi-Bin Hsieh ,  Heng-Chih Lin

IPC分类号： H03M1/38

CPC分类号： H03M1/1245 ,  G11C27/024 ,  G11C27/026 ,  H03K3/356139 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/164 ,  H03M1/44

摘要： A comparator for a pipelined ADC includes a sampling circuit coupled to a plurality of differential input voltages and a plurality of differential reference voltages, for sampling the plurality of differential input voltages according to a first clock signal and sampling the plurality of differential reference voltages according to a second clock signal, a preamplifier coupled to the sampling circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, for amplifying a voltage across the positive input terminal and the negative input terminal for generating a plurality of differential output voltages, and a latch circuit coupled to the preamplifier for latching the plurality of differential output voltages.

摘要翻译： 用于流水线ADC的比较器包括耦合到多个差分输入电压和多个差分参考电压的采样电路，用于根据第一时钟信号对多个差分输入电压进行采样，并根据 第二时钟信号，耦合到采样电路的前置放大器，包括正输入端，负输入端，正输出端和负输出端，用于放大正输入端和负输入端两端的电压，以产生 多个差分输出电压，以及耦合到前置放大器的锁存电路，用于锁存多个差分输出电压。

公开(公告)号：US20110012765A1

公开(公告)日：2011-01-20

申请号：US12549363

申请日：2009-08-28

申请人： Yi-Bin Hsieh ,  Heng-Chih Lin

发明人： Yi-Bin Hsieh ,  Heng-Chih Lin

IPC分类号： H03M3/00 ,  H03M1/36

CPC分类号： H03M1/1245 ,  G11C27/024 ,  G11C27/026 ,  H03K3/356139 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/164 ,  H03M1/44

摘要： A comparator for a pipelined ADC includes a sampling circuit coupled to a plurality of differential input voltages and a plurality of differential reference voltages, for sampling the plurality of differential input voltages according to a first clock signal and sampling the plurality of differential reference voltages according to a second clock signal, a preamplifier coupled to the sampling circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, for amplifying a voltage across the positive input terminal and the negative input terminal for generating a plurality of differential output voltages, and a latch circuit coupled to the preamplifier for latching the plurality of differential output voltages.

摘要翻译： 用于流水线ADC的比较器包括耦合到多个差分输入电压和多个差分参考电压的采样电路，用于根据第一时钟信号对多个差分输入电压进行采样，并根据 第二时钟信号，耦合到采样电路的前置放大器，包括正输入端，负输入端，正输出端和负输出端，用于放大正输入端和负输入端两端的电压，以产生 多个差分输出电压，以及耦合到前置放大器的锁存电路，用于锁存多个差分输出电压。

公开(公告)号：US07693494B2

公开(公告)日：2010-04-06

申请号：US11296148

申请日：2005-12-06

申请人： Petteri M. Litmanen ,  Heng-Chih Lin

发明人： Petteri M. Litmanen ,  Heng-Chih Lin

IPC分类号： H04B1/04 ,  H01Q11/12

CPC分类号： H03G1/0088 ,  H03F1/0205 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/331 ,  H03F2200/366 ,  H03F2203/21145 ,  H03G3/001 ,  H04B1/0483

摘要： A novel digital attenuator circuit and associated pre-power amplifier (PPA) that substantially increases the dynamic range of the amplifier. Increased dynamic range is achieved by placing a digital current attenuator circuit at the output of the pre-power amplifier so that the minimum possible current output of the transistor switch array of the PPA can be further attenuated. The attenuator functions to split the current between the load and the power supply VDD (i.e. AC ground) based on device ratio that is controlled digitally via an input power control word. The digital attenuator is constructed as a segmented digitally controlled matrix or cell array comprising at least a pass and bypass matrix or array. The pass matrix controls the amount of current output from the PPA while the bypass matrix controls the amount of current shorted to the AC ground (i.e. power supply). By varying the number of transistors on or off in each matrix, the power output of the PPA can be easily and accurately controlled.

摘要翻译： 一种新颖的数字衰减器电路和相关的预功率放大器（PPA），其大大增加了放大器的动态范围。 通过将数字电流衰减器电路放置在预功率放大器的输出端，使得PPA的晶体管开关阵列的最小可能的电流输出可以被进一步衰减来实现增加的动态范围。 衰减器用于基于经由输入功率控制字数字地控制的器件比率来分压负载和电源VDD（即，交流地）之间的电流。 数字衰减器被构造为包括至少一个通过和旁路矩阵或阵列的分段数字控制矩阵或单元阵列。 通过矩阵控制从PPA输出的电流量，而旁路矩阵控制短路到交流地（即电源）的电流量。 通过改变每个矩阵中的晶体管的数量，可以容易且准确地控制PPA的功率输出。

公开(公告)号：US20080036506A1

公开(公告)日：2008-02-14

申请号：US11836206

申请日：2007-08-09

申请人： Tin-Sing Lam ,  Chao-Tung Yang ,  Heng-Chih Lin ,  Shou-Fang Chen ,  Sining Zhou

发明人： Tin-Sing Lam ,  Chao-Tung Yang ,  Heng-Chih Lin ,  Shou-Fang Chen ,  Sining Zhou

IPC分类号： G01R23/02

CPC分类号： G06F1/08 ,  H03L7/099

摘要： A frequency switching method is used to make switching among a plurality of frequency signal sources each providing a specific frequency range covering multiple bands. The method includes steps of providing a target frequency data; selecting one of the frequency signal sources to output a first clock signal; generating a first frequency data according to the clock signal of the first frequency to compare with the target frequency data; outputting a second clock signal with the highest band of another one of the frequency signal sources possessing a frequency range higher than that of the selected frequency signal source when the target frequency data is greater than the first frequency data; and outputting the second clock signal with the lowest band of the selected frequency signal source when the target frequency data is smaller than the first frequency data.

摘要翻译： 频率切换方法用于在多个频率信号源之间进行切换，每个频率信号源提供覆盖多个频带的特定频率范围。 该方法包括提供目标频率数据的步骤; 选择频率信号源之一以输出第一时钟信号; 根据所述第一频率的时钟信号产生第一频率数据，以与所述目标频率数据进行比较; 当所述目标频率数据大于所述第一频率数据时，输出具有所述频率信号源中的另一个的最高频带的第二时钟信号，所述频率信号源具有高于所选择的频率信号源的频率范围的频率范围; 以及当所述目标频率数据小于所述第一频率数据时，将所述第二时钟信号输出到所选频率信号源的最低频带。

公开(公告)号：US07187917B2

公开(公告)日：2007-03-06

申请号：US10811584

申请日：2004-03-29

申请人： Heng-Chih Lin ,  Ranjit Gharpurey

发明人： Heng-Chih Lin ,  Ranjit Gharpurey

IPC分类号： H04B1/26

CPC分类号： H03B27/00 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0033 ,  H03D2200/0086

摘要： A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal 231. The circuit has an oscillator circuit 210 and a harmonic rejection mixer (HRM) 230. The oscillator circuit 210 includes at least one “circuit portion” (FIG. 2A) configured to receive first and second orthogonal oscillator input signals (two of I, I−, Q, Q−) having respective first and second phases, and to provide an arbitrarily large number of oscillator output signals (φM) having respective mutually distinct phases that are interpolated between the first and second phases. Harmonic rejection mixer 230 is configured to use the input signal to modulate a combination of the oscillator output signals, the oscillator output signals being respectively weighted so as to provide an emulated sinusoidal signal constituting the reduced harmonic content output signal.

摘要翻译： 电路提供根据输入信号231调制的减少的谐波含量输出信号OUTA和/或OUTB。 电路具有振荡电路210和谐波抑制混频器（HRM）230。 振荡器电路210包括至少一个“电路部分”（图2A），其被配置为接收具有相应的第一和第二相位的第一和第二正交振荡器输入信号（I，I，I，Q-中的两个），并且 提供任意大量的振荡器输出信号（phiM），其具有在第一和第二相之间插值的各自相互不同的相位。 谐波抑制混频器230被配置为使用输入信号来调制振荡器输出信号的组合，振荡器输出信号被分别加权，以便提供构成还原谐波内容输出信号的仿真正弦信号。

公开(公告)号：US07187909B2

公开(公告)日：2007-03-06

申请号：US10811704

申请日：2004-03-29

申请人： Heng-Chih Lin ,  Ranjit Gharpurey ,  Paul A. Fontaine

发明人： Heng-Chih Lin ,  Ranjit Gharpurey ,  Paul A. Fontaine

IPC分类号： H04B1/02 ,  H04B17/00

CPC分类号： H03F3/24 ,  H03F3/345 ,  H04B1/04

摘要： A current-domain transmitter is configured to receive an input signal and provide a transmitted signal. The transmitter has a plurality of elements, operatively arranged between the input signal and the transmitted signal and configured to represent the input signal with respective electric currents whose respective current magnitudes are each substantially proportional to the input signal. The elements may include a current-steering digital-to-analog converter (DAC), a current mode filter (such as an LPF), a current mode mixer, and/or a current mode amplifier.

摘要翻译： 当前域发射机被配置为接收输入信号并提供发射信号。 发射机具有多个元件，可操作地布置在输入信号和发射信号之间，并被配置为用相应的电流表示输入信号，其各自的电流幅度大致与输入信号成比例。 元件可以包括电流转向数模转换器（DAC），电流模式滤波器（例如LPF），电流模式混频器和/或电流模式放大器。

公开(公告)号：US20060152288A1

公开(公告)日：2006-07-13

申请号：US11031185

申请日：2005-01-07

申请人： Solti Peng ,  Chien-Chung Chen ,  Abdellatif Bellaouar ,  Heng-Chih Lin

发明人： Solti Peng ,  Chien-Chung Chen ,  Abdellatif Bellaouar ,  Heng-Chih Lin

IPC分类号： H03F1/22

CPC分类号： H03F1/30 ,  H03F3/189 ,  H03F2200/18 ,  H03F2200/456 ,  H03F2200/72

摘要： According to one embodiment of the invention, an amplifier includes a gate bias circuit operable to generate a gate bias voltage and a common gate amplifier that includes a transistor having a gate biased by an output of the gate bias circuit and also having a source connected to an inductor for providing a path to ground for direct current flowing through the transistor. According to another embodiment of the invention, a method for amplifying a signal by an amplifier includes generating a gate bias voltage indicative of a difference between a reference voltage and an output voltage of the amplifier, biasing the gate of the common-gate amplifier with the gate bias voltage, and blocking, by a passive device, alternating current signals from flowing from the source of the transistor to ground.

摘要翻译： 根据本发明的一个实施例，放大器包括栅极偏置电路，其可操作以产生栅极偏置电压和公共栅极放大器，该公共栅极放大器包括具有由栅极偏置电路的输出偏置的栅极的晶体管，并且源极连接到 电感器，用于为直流电流流过晶体管提供路径。 根据本发明的另一个实施例，一种用于放大放大器的信号的方法包括：生成指示放大器的参考电压和输出电压之间的差异的栅极偏置电压，使公共栅极放大器的栅极偏置 栅极偏置电压和被无源器件阻塞从晶体管的源极流到地的交流信号。

公开(公告)号：US20050225464A1

公开(公告)日：2005-10-13

申请号：US10821576

申请日：2004-04-09

申请人： Heng-Chih Lin ,  Chien-Chung Chen

发明人： Heng-Chih Lin ,  Chien-Chung Chen

IPC分类号： H03M1/66 ,  H03M1/74

CPC分类号： H03M1/0614 ,  H03M1/662 ,  H03M1/742

摘要： An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage devices 301 . . . configured to sample and store the digital input signal at different respective phases of a clock signal. The arrangement also has plural current steering digital-to-analog converters (DACs) 311 . . . configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals. The arrangement also includes a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.

摘要翻译： 一种布置提供了表示数字输入信号的值的减少谐波含量输出信号。 该装置包括多个存储装置301。 。 。 配置成在时钟信号的不同相位采样和存储数字输入信号。 该装置还具有多个电流转向数模转换器（DAC）311。 。 。 被配置为从多个存储设备中的相应存储设备接收相应的存储的数字信号，并且提供表示所接收的存储的数字信号的相应电流。 该装置还包括组合装置，其被配置为组合来自多个电流导向DAC中的相应电流的电流，以便提供表示数字输入信号的值的减少的谐波含量输出信号。

公开(公告)号：US20050212599A1

公开(公告)日：2005-09-29

申请号：US10806962

申请日：2004-03-23

申请人： Heng-Chih Lin ,  Ranjit Gharpurey

发明人： Heng-Chih Lin ,  Ranjit Gharpurey

IPC分类号： H03F3/45

CPC分类号： H03F3/45659 ,  H03F2200/453

摘要： The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

摘要翻译： 具有自适应放大器输出共模电压调节的电路包括：差分前置放大器; 重新产生的比较器，其具有耦合到前置放大器的差分输出的差分输入; 以及耦合到前置放大器的共模节点的复制比较器，用于调整前置放大器的共模。 复制比较器提供了一个跳变点参考，用于设置前置放大器的输出共模。 这将前置放大器的输出共模设置为重新产生的比较器的最敏感区域。

公开(公告)号：US20050134327A1

公开(公告)日：2005-06-23

申请号：US10743571

申请日：2003-12-22

申请人： Jin-sheng Wang ,  Heng-Chih Lin ,  Chien-Chung Chen

发明人： Jin-sheng Wang ,  Heng-Chih Lin ,  Chien-Chung Chen

IPC分类号： G01R19/165 ,  H03K5/153

CPC分类号： G01R19/16557

摘要： A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.

摘要翻译： 高速信号电平检测器采用逆变器的高增益和高带宽进行比较。 高速信号电平检测器能够实现期望的高速电平检测，而不需要使用平均技术或高带宽运算放大器型比较器所需的实质功耗。