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公开(公告)号：US12027136B2
公开(公告)日：2024-07-02
申请号：US18147219
申请日：2022-12-28
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Jangjin Nam , Dongmyung Lee , Donghoon Baek , Daejoon Lee
IPC: G09G5/00
CPC classification number: G09G5/003 , G09G2370/04
Abstract: Provided is a data transmission method, including: sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform clock calibration; sending first configuration information to the source driver chip over a data channel in response to completing the clock calibration by the source driver chip, wherein the first configuration information instructs the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.
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公开(公告)号：US20230290297A1
公开(公告)日：2023-09-14
申请号：US18170759
申请日：2023-02-17
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Dongmyung LEE , Donghoon BAEK , Jangjin NAM , Enwei NI
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G5/393 , G09G2310/0275 , G09G2320/0252 , G09G2330/021 , G09G2330/06 , G09G2370/08 , G09G2370/10 , G09G2370/16
Abstract: A control method for a data driver, a control method for a timing controller, a data driver control apparatus, a timing controller, an electronic device, and a storage medium are provided. The control method for the data driver includes: obtaining a data comparison signal, where the data comparison signal represents a comparison relationship between first display data for enabling a first pixel row to display and second display data for enabling a second pixel row to display, and in time, the second pixel row is driven to display after the first pixel row is driven to display; and controlling an operation state of the data driver according to the data comparison signal.
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公开(公告)号：US12218699B2
公开(公告)日：2025-02-04
申请号：US18003724
申请日：2021-12-01
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Zhengbei Hua , Dongmyung Lee , Jangjin Nam , Donghoon Baek , Hao Fan
IPC: H04B1/18 , H04L41/0896
Abstract: The present disclosure provides a receiver circuit and a receiver circuit control method. In the present disclosure, the input data is detected by a detection circuit to obtain a data rate detection result, and the bandwidth of the receiver is automatically adjusted according to the data rate detection result.
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公开(公告)号：US12080211B2
公开(公告)日：2024-09-03
申请号：US18146891
申请日：2022-12-27
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Jangjin Nam , Dongmyung Lee , Donghoon Baek , Daejoon Lee
CPC classification number: G09G3/20 , G09G3/36 , G09G2310/0272 , G09G2310/061 , G09G2310/08 , G09G2330/023
Abstract: Provided is a timing controller. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.
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公开(公告)号：US20230216487A1
公开(公告)日：2023-07-06
申请号：US18081922
申请日：2022-12-15
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Xiaoheng Zhang , Jiajhang Wu , Haohao Zhang
IPC: H03K3/356 , H03K19/0185
CPC classification number: H03K3/356113 , H03K19/018521 , H03K3/356182
Abstract: The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.
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Patent Agency Ranking
公开(公告)号：US20250014501A1
公开(公告)日：2025-01-09
申请号：US18898425
申请日：2024-09-26
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Jangjin NAM , Dongmyung LEE , Donghoon BAEK , Daejoon LEE
IPC: G09G3/20
Abstract: Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain. Prior to transmitting the equalization matching data to the source driver chip upon sending the link stable pattern to the source driver chip, the method further includes transmitting equalization gain configuration information to the source driver chip.
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公开(公告)号：US12033562B2
公开(公告)日：2024-07-09
申请号：US18170759
申请日：2023-02-17
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Dongmyung Lee , Donghoon Baek , Jangjin Nam , Enwei Ni
CPC classification number: G09G3/2096 , G09G5/393 , G09G2310/0275 , G09G2320/0252 , G09G2330/021 , G09G2330/06 , G09G2370/08 , G09G2370/10 , G09G2370/16
Abstract: A control method for a data driver, a control method for a timing controller, a data driver control apparatus, a timing controller, an electronic device, and a storage medium are provided. The control method for the data driver includes: obtaining a data comparison signal, where the data comparison signal represents a comparison relationship between first display data for enabling a first pixel row to display and second display data for enabling a second pixel row to display, and in time, the second pixel row is driven to display after the first pixel row is driven to display; and controlling an operation state of the data driver according to the data comparison signal.
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公开(公告)号：US11961451B2
公开(公告)日：2024-04-16
申请号：US18147997
申请日：2022-12-29
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Jangjin Nam , Dongmyung Lee , Donghoon Baek , Daejoon Lee
CPC classification number: G09G3/2096 , G06F1/04 , G06F1/08 , G06F1/12 , G06F1/14 , G09G3/2092 , G09G2310/0275 , G09G2310/08 , G09G2320/0693 , G09G2330/021 , G09G2340/0435 , G09G2370/08 , G09G2370/14
Abstract: Provided is a data transmission method in a timing controller. The data transmission method includes sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform a clock calibration; successively sending, in response to completing the clock calibration by the source driver chip, a first identification code and an initialization control instruction to the source driver chip over a data channel, wherein the first identification code indicates a start of transmission of the initialization control instruction, and the initialization control instruction comprises configuration information, the configuration information instructing the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.
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公开(公告)号：US20230386380A1
公开(公告)日：2023-11-30
申请号：US18146891
申请日：2022-12-27
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Jangjin NAM , Dongmyung LEE , Donghoon BAEK , Daejoon LEE
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/08 , G09G2310/0272 , G09G2330/023 , G09G2310/061 , G09G3/36
Abstract: Provided is a timing controller. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.
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公开(公告)号：US20230231590A1
公开(公告)日：2023-07-20
申请号：US18003724
申请日：2021-12-01
Applicant: Beijing ESWIN Computing Technology Co., Ltd. , Hefei ESWIN Computing Technology Co., Ltd.
Inventor： Zhengbei Hua , Dongmyung Lee , Jangjin Nam , Donghoon Baek , Hao Fan
CPC classification number: H04B1/18 , H04B1/406 , H04L41/0896
Abstract: The present disclosure provides a receiver circuit and a receiver circuit control method. In the present disclosure, the input data is detected by a detection circuit to obtain a data rate detection result, and the bandwidth of the receiver is automatically adjusted according to the data rate detection result.
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