公开(公告)号：US08111342B2

公开(公告)日：2012-02-07

申请号：US12129198

申请日：2008-05-29

Applicant: Shin-Tack Kang ,  Jong-Huan Lee ,  Hong-Woo Lee ,  Hyeon-Hwan Kim ,  Byeong-Jae Ahn ,  Gyu-Tae Kim ,  Jong-Woong Chang ,  Jong-Hyuk Lee

Inventor： Shin-Tack Kang ,  Jong-Huan Lee ,  Hong-Woo Lee ,  Hyeon-Hwan Kim ,  Byeong-Jae Ahn ,  Gyu-Tae Kim ,  Jong-Woong Chang ,  Jong-Hyuk Lee

IPC: G02F1/136 ,  G02F1/1335

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/136222 ,  H01L29/4908

Abstract: A display substrate that has increased aperture ratio is presented. The display substrate includes a base substrate, a first metal pattern formed on the base substrate and a gate wiring and a gate electrode. A first insulating layer is formed on the base substrate covering the first metal pattern. A second metal pattern is formed on the first insulating layer including a data wiring crossing the gate wiring, a source electrode connected to the data wiring and a drain electrode separated from the source electrode. A second insulating layer is formed on the base substrate covering the second metal pattern. A transparent electrode is formed on the second insulating layer. An organic layer is formed on the transparent electrode, and a pixel electrode is formed on the organic layer being insulated with the transparent electrode, and contacted to the drain electrode. The organic layer may comprise red, green and blue color filters.

Abstract translation: 提出了一种具有增加孔径比的显示基板。 显示基板包括基底基板，形成在基底基板上的第一金属图案以及栅极布线和栅极电极。 在覆盖第一金属图案的基底基板上形成第一绝缘层。 在第一绝缘层上形成第二金属图案，该第一绝缘层包括与栅极布线交叉的数据布线，连接到数据布线的源电极和与源电极分离的漏电极。 在覆盖第二金属图案的基底基板上形成第二绝缘层。 在第二绝缘层上形成透明电极。 在透明电极上形成有机层，在与透明电极绝缘的有机层上形成像素电极，并与漏电极接触。 有机层可以包括红色，绿色和蓝色滤色器。

公开(公告)号：US07951698B2

公开(公告)日：2011-05-31

申请号：US11947139

申请日：2007-11-29

Applicant: Seung Eon Moon ,  Eun Kyoung Kim ,  Hong Yeol Lee ,  Jong Hyurk Park ,  Kang Ho Park ,  Jong Dae Kim ,  So Jeong Park ,  Gyu Tae Kim

Inventor： Seung Eon Moon ,  Eun Kyoung Kim ,  Hong Yeol Lee ,  Jong Hyurk Park ,  Kang Ho Park ,  Jong Dae Kim ,  So Jeong Park ,  Gyu Tae Kim

IPC: H01L45/00 ,  H01L21/00

CPC classification number: H01L21/76892 ,  H01L2221/1094

Abstract: A method of fabricating an electronic device using nanowires, minimizing the number of E-beam processing steps and thus improving a yield, includes the steps of: forming electrodes on a substrate; depositing a plurality of nanowires on the substrate including the electrodes; capturing an image of the substrate including the nanowires and the electrodes; drawing virtual connection lines for connecting the nanowires with the electrodes on the image using an electrode pattern simulated through a computer program, after capturing the image; coating an E-beam photoresist on the substrate; removing the photoresist from regions corresponding to the virtual connection lines and the electrode pattern using E-beam lithography; depositing a metal layer on the substrate after removing the photoresist from the regions of the virtual connection lines; and removing remaining photoresist from the substrate using a lift-off process.

Abstract translation: 使用纳米线制造电子器件的方法，使电子束处理步骤的数量最小化并因此提高产量，包括以下步骤：在衬底上形成电极; 在包括电极的基板上沉积多个纳米线; 捕获包括纳米线和电极的衬底的图像; 绘制虚拟连接线，用于在捕获图像之后，使用通过计算机程序模拟的电极图案将纳米线与图像上的电极连接; 在基板上涂覆电子束光致抗蚀剂; 使用电子束光刻从与虚拟连接线对应的区域和电极图案中去除光致抗蚀剂; 在从虚拟连接线的区域去除光致抗蚀剂之后，在基板上沉积金属层; 以及使用剥离工艺从衬底去除剩余的光致抗蚀剂。

公开(公告)号：US20080297677A1

公开(公告)日：2008-12-04

申请号：US12129198

申请日：2008-05-29

Applicant: Shin-Tack KANG ,  Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Gyu-Tae KIM

Inventor： Shin-Tack KANG ,  Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Gyu-Tae KIM

IPC: G02F1/136 ,  H01L21/84

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/136222 ,  H01L29/4908

Abstract: A display substrate that has increased aperture ratio is presented. The display substrate includes a base substrate, a first metal pattern formed on the base substrate and a gate wiring and a gate electrode. A first insulating layer is formed on the base substrate covering the first metal pattern. A second metal pattern is formed on the first insulating layer including a data wiring crossing the gate wiring, a source electrode connected to the data wiring and a drain electrode separated from the source electrode. A second insulating layer is formed on the base substrate covering the second metal pattern. A transparent electrode is formed on the second insulating layer. An organic layer is formed on the transparent electrode, and a pixel electrode is formed on the organic layer being insulated with the transparent electrode, and contacted to the drain electrode. The organic layer may comprise red, green and blue color filters.

Abstract translation: 提出了一种具有增加孔径比的显示基板。 显示基板包括基底基板，形成在基底基板上的第一金属图案以及栅极布线和栅极电极。 在覆盖第一金属图案的基底基板上形成第一绝缘层。 在第一绝缘层上形成第二金属图案，该第一绝缘层包括与栅极布线交叉的数据布线，连接到数据布线的源电极和与源电极分离的漏电极。 在覆盖第二金属图案的基底基板上形成第二绝缘层。 在第二绝缘层上形成透明电极。 在透明电极上形成有机层，在与透明电极绝缘的有机层上形成像素电极，并与漏电极接触。 有机层可以包括红色，绿色和蓝色滤色器。

公开(公告)号：US20080213567A1

公开(公告)日：2008-09-04

申请号：US11951119

申请日：2007-12-05

Applicant: Jonghyurk PARK ,  Eunkyoung KIM ,  Seungeon MOON ,  Hong-Yeol LEE ,  Kang-Ho PARK ,  Jong Dae KIM ,  Gyu-Tae KIM ,  Kang-Ho LEE ,  Seong-Min LEE

Inventor： Jonghyurk PARK ,  Eunkyoung KIM ,  Seungeon MOON ,  Hong-Yeol LEE ,  Kang-Ho PARK ,  Jong Dae KIM ,  Gyu-Tae KIM ,  Kang-Ho LEE ,  Seong-Min LEE

IPC: B32B5/16 ,  B05D1/12

CPC classification number: B41J2/14314 ,  F03G7/005 ,  Y10T428/25

Abstract: Provided is a hetero-junction membrane including: a first layer comprising first nanoparticles of a first conductive type; and a second layer comprising second nanoparticles of a second conductive type, wherein the first layer and the second layer are joined to each other. The hetero-junction membrane has advantages in that actuating efficiency is much higher, the direction of actuating can be predicted and the manufacturing processes are simple compared to conventional bucky paper formed of a single layer.

Abstract translation: 提供了一种异质结膜，包括：第一层，包括第一导电类型的第一纳米颗粒; 以及包括第二导电类型的第二纳米颗粒的第二层，其中所述第一层和所述第二层彼此连接。 异相结合膜的优点在于，与由单层形成的传统的凹版纸相比，致动效率高得多，可以预测致动的方向，并且制造工艺简单。

公开(公告)号：US20130141318A1

公开(公告)日：2013-06-06

申请号：US13485243

申请日：2012-05-31

Applicant: Beom-Jun KIM ,  Myung-Koo HUR ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Myung-Sub LEE ,  Gyu-Tae KIM

Inventor： Beom-Jun KIM ,  Myung-Koo HUR ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Myung-Sub LEE ,  Gyu-Tae KIM

IPC: G09G3/36 ,  H03K17/693

CPC classification number: G09G3/3688 ,  G09G3/36 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0251 ,  G09G2310/0291 ,  G09G2310/08 ,  G11C19/28 ,  H03K17/693

Abstract: A gate driving circuit is provided which includes a plurality of stages cascade-connected with each other and outputting a plurality of gate signals. An n-th (n is a natural number) stage includes a gate output part, a first node control part and a carry part. The gate output part includes a first transistor. The first transistor outputs a high voltage of a clock signal to a high voltage of an n-th gate signal in response to a high voltage of a control node. The first node control part is connected to the control node to control a signal of the control node and includes at least one transistor having a channel longer than the channel length of the first transistor. The carry part outputs the high voltage of the clock signal to an n-th carry signal in response to the signal of the control node.

Abstract translation: 提供一种栅极驱动电路，其包括彼此级联的多个级并输出多个栅极信号。 第n（n是自然数）级包括门输出部分，第一节点控制部分和进位部分。 栅极输出部分包括第一晶体管。 第一晶体管响应于控制节点的高电压而将时钟信号的高电压输出到第n栅极信号的高电压。 第一节点控制部分连接到控制节点以控制控制节点的信号，并且包括至少一个具有比第一晶体管的沟道长度更长的沟道的晶体管。 进位部分响应于控制节点的信号将时钟信号的高电压输出到第n进位信号。

公开(公告)号：US20090195869A1

公开(公告)日：2009-08-06

申请号：US11940379

申请日：2007-11-15

Applicant: Eun Kyoung Kim ,  Seung Eon Moon ,  Hong Yeol Lee ,  Jong Hyurk Park ,  Kang Ho Park ,  Jong Dae Kim ,  Gyu Tae Kim ,  Do Young Jang ,  Eung Seok Park ,  Hyun Jin Ji

Inventor： Eun Kyoung Kim ,  Seung Eon Moon ,  Hong Yeol Lee ,  Jong Hyurk Park ,  Kang Ho Park ,  Jong Dae Kim ,  Gyu Tae Kim ,  Do Young Jang ,  Eung Seok Park ,  Hyun Jin Ji

IPC: G02B21/06 ,  G06K9/00

CPC classification number: G02B21/06 ,  G01N21/21 ,  G02B21/365 ,  G02B27/286 ,  Y10S977/881

Abstract: Provided is an optical microscope system for detecting nanowires that is designed with a rotational polarizer and Fast Fourier Transform (FFT) to allow for use of an existing optical microscope in fabricating an electronic device having the nanowires. The optical microscope system includes: a light source for emitting light to provide the light to a nanowire sample; a rotational polarizer provided on a path of the light emitted from the light source for polarizing the light; an optical microscope for detecting a nanowire image using light that is polarized by the rotational polarizer and incident on the nanowire sample; a CCD camera provided in a region of the optical microscope for photographing and storing the nanowire image detected by the optical microscope; and a data processor for performing Fast Fourier Transform (FFT) on the nanowire image stored in the CCD camera. Intensity of reflected light varies, due to optical anisotropy of the nanowires, along a polarizing orientation of light incident on the nanowires. It is possible to obtain a distinct image of the nanowires having a nanometer line width by performing FFT on each pixel of reflected light images obtained at predetermined time intervals after light passing through the polarizer rotating in a predetermined period is incident on the nanowires.

Abstract translation: 提供了一种用于检测纳米线的光学显微镜系统，其被设计为具有旋转偏振器和快速傅里叶变换（FFT），以允许使用现有的光学显微镜来制造具有纳米线的电子器件。 光学显微镜系统包括：用于发射光以向纳米线样品提供光的光源; 设置在从光源发射的光的路径上以使光偏振的旋转偏振器; 光学显微镜，用于使用被旋转偏振器偏振并入射在纳米线样品上的光检测纳米线图像; 设置在光学显微镜的区域中的CCD照相机，用于拍摄和存储由光学显微镜检测的纳米线图像; 以及用于在存储在CCD照相机中的纳米线图像上执行快速傅里叶变换（FFT）的数据处理器。 反射光的强度由于纳米线的光学各向异性而沿着入射在纳米线上的光的偏振方向而变化。 通过在经过预定时间内旋转的偏振片的光入射到纳米线上之后，以预定时间间隔获得的反射光图像的每个像素执行FFT，可以获得具有纳米线宽度的纳米线的不同图像。

公开(公告)号：US20090189679A1

公开(公告)日：2009-07-30

申请号：US12338182

申请日：2008-12-18

Applicant: Hong-Woo Lee ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim ,  Gyu-Tae Kim ,  Kyoung-Jun Jang

Inventor： Hong-Woo Lee ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim ,  Gyu-Tae Kim ,  Kyoung-Jun Jang

IPC: H03K17/687 ,  G02F1/1368

CPC classification number: G09G3/3677 ,  G11C19/184 ,  H03K17/165

Abstract: A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

Abstract translation: 栅极驱动电路包括级联级，每级包括上拉部分，进位部分，上拉驱动部分，保持部分和逆变器。 上拉部分将输入时钟的栅极电压上拉。 进位部分将输入电压提升到输入时钟。 上拉驱动部分连接到与进位部分和上拉部分相同的控制端子（Q-节点），并且从前一级接收先前的进位电压以打开上拉部分和进位 部分。 保持部将栅极电压保持在截止电压，逆变器基于逆变器时钟来控制保持部的开启和关闭保持部中的至少一个。 给定水平周期（1H）中的高电平的反相器时钟在时间上在预定时间间隔的输入时钟的高电平之前。

公开(公告)号：US20090167733A1

公开(公告)日：2009-07-02

申请号：US12332213

申请日：2008-12-10

Applicant: Bong-Jun Lee ,  Byeong-Jae Ahn ,  Yeo-Geon Yoon ,  Hong-Woo Lee ,  Hyuk-Jin Kim ,  Jong-Oh Kim ,  Gyu-Tae Kim

Inventor： Bong-Jun Lee ,  Byeong-Jae Ahn ,  Yeo-Geon Yoon ,  Hong-Woo Lee ,  Hyuk-Jin Kim ,  Jong-Oh Kim ,  Gyu-Tae Kim

IPC: G09G5/00

CPC classification number: H01L27/124 ,  H01L27/1288

Abstract: A display substrate includes a base substrate, a first line, a second line, a bridge line, a thin-film transistor (TFT), a storage line, and a pixel electrode. The first line extends in a first direction on the base substrate. The second line extends in a second direction on the base substrate and is divided into two portions with respect to the first line. The bridge line makes contact with the two portions of the second line in first and second bridge contact regions. The TFT includes a source electrode making contact with one of the first and second lines in a data contact region. The storage line is formed on the one of the first and second lines. The pixel electrode is formed on the storage line and is electrically connected to the TFT. The display substrate reduces formation of parasitic capacitance between pixel electrode and data line.

Abstract translation: 显示基板包括基底基板，第一线，第二线，桥接线，薄膜晶体管（TFT），存储线和像素电极。 第一线在基底基板上沿第一方向延伸。 第二线在基底基板上沿第二方向延伸，并且相对于第一线分成两部分。 桥接线与第一和第二桥接触区域中的第二线路的两个部分接触。 TFT包括与数据接触区域中的第一和第二线路之一接触的源电极。 存储线形成在第一和第二线之一上。 像素电极形成在存储线上并与TFT电连接。 显示基板减少像素电极和数据线之间的寄生电容的形成。

公开(公告)号：US20080233675A1

公开(公告)日：2008-09-25

申请号：US11927881

申请日：2007-10-30

Applicant: Hong Yeol Lee ,  Seung Eon Moon ,  Eun Kyoung Kim ,  Jong Hyurk Park ,  Kang Ho Park ,  Jong Dae Kim ,  Gyu Tae Kim ,  Jae Woo Lee ,  Hye Yeon Ryu ,  Jung Hwan Huh

Inventor： Hong Yeol Lee ,  Seung Eon Moon ,  Eun Kyoung Kim ,  Jong Hyurk Park ,  Kang Ho Park ,  Jong Dae Kim ,  Gyu Tae Kim ,  Jae Woo Lee ,  Hye Yeon Ryu ,  Jung Hwan Huh

IPC: H01L21/00

CPC classification number: H01L29/0673 ,  H01L21/76289 ,  H01L27/1225 ,  H01L29/0665 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  Y10S977/762

Abstract: Provided is a method of fabricating a nano-wire array, including the steps of: depositing a nano-wire solution, which contains nano-wires, on a substrate; forming a first etch region in a stripe shape on the substrate and then patterning the nano-wires; forming drain and source electrode lines parallel to each other with the patterned nano-wires interposed therebetween; forming a plurality of drain electrodes which have one end connected to the drain electrode line and contact at least one of the nano-wires, and forming a plurality of source electrodes, which have one end connected to the source electrode line and contact the nano-wires that contact the drain electrodes; forming a second etch region between pairs of the drain and source electrodes so as to prevent electrical contacts between the pairs of the drain and source electrodes; forming an insulating layer on the substrate; and forming a gate electrode between the drain and source electrodes contacting the nano-wires on the insulating layer. Accordingly, even in an unparallel structure of nano-wires to electrode lines, a large scale nano-wire array is practicable and applicable to an integrated circuit or display unit with nano-wire alignment difficulty, as well as to device applications using flexible substrates.

Abstract translation: 提供一种制造纳米线阵列的方法，包括以下步骤：在衬底上沉积包含纳米线的纳米线溶液; 在衬底上形成带状的第一蚀刻区域，然后对纳米线进行构图; 形成彼此平行的漏极和源极电极线，其间插入图案化的纳米线; 形成多个漏电极，所述多个漏电极的一端连接到所述漏电极线并接触所述纳米线中的至少一个，并且形成多个源电极，所述多个源电极的一端连接到所述源电极线并接触所述纳米线， 接触漏电极的电线; 在所述漏极和源极电极之间形成第二蚀刻区域，以防止所述漏极和源极电极之间的电接触; 在所述基板上形成绝缘层; 以及在与绝缘层上的纳米线接触的漏极和源电极之间形成栅电极。 因此，即使在纳米线与电极线的不平行结构中，大规模的纳米线阵列也是可行的并且适用于具有纳米线对准困难的集成电路或显示单元以及使用柔性基板的器件应用。

公开(公告)号：US06784779B2

公开(公告)日：2004-08-31

申请号：US09888559

申请日：2001-06-26

Applicant: Jin Koog Shin ,  Gyu Tae Kim ,  Hak Su Kim

Inventor： Jin Koog Shin ,  Gyu Tae Kim ,  Hak Su Kim

IPC: H01F500

CPC classification number: H01F17/0006 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  D01F9/127 ,  Y10S977/932

Abstract: Disclosed is an inductor, which employs carbon nanotubes and/or carbon nanofibers synthesized in a shape of coils, so that the inductor has a high inductance even in a minute circuit of a nano-size or a micro-size. The inductor may have a carbon nanotube and/or carbon nanofiber synthesized in a shape of a coil, in which the carbon nanotube and/or carbon nanofiber is synthesized between catalysts fixed at desired locations on

Abstract translation: 公开了一种电感器，其采用以线圈形式合成的碳纳米管和/或碳纳米纤维，使得即使在纳米尺寸或微尺寸的微小电路中，电感器也具有高电感。 电感器可以具有以线圈形式合成的碳纳米管和/或碳纳米纤维，其中碳纳米管和/或碳纳米纤维在固定在期望位置上的催化剂之间合成