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10 条记录 (耗时 0.012 秒)

    SEMICONDUCTOR AND METHOD
    2.
    发明申请
    SEMICONDUCTOR AND METHOD 有权
    半导体和方法

    公开(公告)号：US20090160470A1

    公开(公告)日：2009-06-25

    申请号：US11963073

    申请日：2007-12-21

    申请人： Franz Reinwald ,  Gerhard Zojer

    发明人： Franz Reinwald ,  Gerhard Zojer

    IPC分类号： G01R31/26 ,  H01L21/66

    CPC分类号： G01R31/2891 ,  G01R31/2884 ,  H01L22/34

    摘要： A semiconductor and method is disclosed. One embodiment includes a detector arrangement to detect the position of a connection element. A probe tip, the detector arrangement including first connection pads are arranged on a substrate surface. A first circuit is connected to the first connection pads.

    摘要翻译： 公开了半导体和方法。 一个实施例包括用于检测连接元件的位置的检测器装置。 包括第一连接垫的检测器装置布置在基板表面上。 第一电路连接到第一连接焊盘。

    Integrated Circuit Including Interconnect Levels
    4.
    发明申请
    Integrated Circuit Including Interconnect Levels 有权
    集成电路包括互连级别

    公开(公告)号：US20120049373A1

    公开(公告)日：2012-03-01

    申请号：US12861877

    申请日：2010-08-24

    申请人： Herbert Gietler ,  Gerhard Zojer ,  Benjamin Finke

    发明人： Herbert Gietler ,  Gerhard Zojer ,  Benjamin Finke

    IPC分类号： H01L23/532 ,  H01L23/528

    CPC分类号： H01L23/5384 ,  H01L23/4824 ,  H01L23/522 ,  H01L24/06 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

    摘要： An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.

    摘要翻译： 如本文所述的集成电路包括包括连续上部互连区域的上部互连级别，连续的上部互连区域包括多个上部接触开口。 集成电路还包括下连接级，其包括连续的下互连区域，连续的下互连区域包括多个下接触开口。 第一触点延伸穿过下接触开口到上互连区域，第二接触开口延伸通过上接触开口到下互连区域。

    Method and device for position detection using connection pads
    5.
    发明授权
    Method and device for position detection using connection pads 有权
    使用连接垫进行位置检测的方法和装置

    公开(公告)号：US07759955B2

    公开(公告)日：2010-07-20

    申请号：US11963073

    申请日：2007-12-21

    申请人： Franz Reinwald ,  Gerhard Zojer

    发明人： Franz Reinwald ,  Gerhard Zojer

    IPC分类号： G01R31/02 ,  G01R31/26

    CPC分类号： G01R31/2891 ,  G01R31/2884 ,  H01L22/34

    摘要： A semiconductor and method is disclosed. One embodiment includes a detector arrangement to detect the position of a connection element. A probe tip, the detector arrangement including first connection pads are arranged on a substrate surface. A first circuit is connected to the first connection pads.

    摘要翻译： 公开了半导体和方法。 一个实施例包括用于检测连接元件的位置的检测器装置。 包括第一连接垫的检测器装置布置在基板表面上。 第一电路连接到第一连接焊盘。

    Semiconductor Chip and Semiconductor Arrangement
    7.
    发明申请
    Semiconductor Chip and Semiconductor Arrangement 有权
    半导体芯片和半导体布置

    公开(公告)号：US20130249018A1

    公开(公告)日：2013-09-26

    申请号：US13427344

    申请日：2012-03-22

    申请人： Gerhard Zojer ,  Daniel Auer ,  Gerrit Utz ,  Claudia Kabusch

    发明人： Gerhard Zojer ,  Daniel Auer ,  Gerrit Utz ,  Claudia Kabusch

    IPC分类号： H01L27/088 ,  H01L27/06

    CPC分类号： H01L27/0296 ,  B60R21/017 ,  H01L23/367 ,  H01L27/0211 ,  H01L27/0629 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One aspect of the invention relates to a semiconductor chip with a semiconductor body. The semiconductor body has an inner region and a ring-shaped outer region. An electronic structure is monolithically integrated in the inner region and has a controllable first semiconductor component with a first load path and a first control input for controlling the first load path. Further, a ring-shaped second electronic component is monolithically integrated in the outer region and surrounds the inner region. Moreover, the second electronic component has a second load path that is electrically not connected in parallel to the first load path.

    摘要翻译： 本发明的一个方面涉及具有半导体本体的半导体芯片。 半导体本体具有内部区域和环形外部区域。 电子结构单片集成在内部区域中并且具有可控制的第一半导体部件，具有第一负载路径和用于控制第一负载路径的第一控制输入。 此外，环状的第二电子部件被整体地集成在外部区域中并且围绕内部区域。 此外，第二电子部件具有与第一负载路径并联电连接的第二负载路径。

    Integrated circuit including interconnect levels
    8.
    发明授权
    Integrated circuit including interconnect levels 有权
    集成电路包括互连级别

    公开(公告)号：US08378491B2

    公开(公告)日：2013-02-19

    申请号：US12861877

    申请日：2010-08-24

    申请人： Herbert Gietler ,  Gerhard Zojer ,  Benjamin Finke

    发明人： Herbert Gietler ,  Gerhard Zojer ,  Benjamin Finke

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5384 ,  H01L23/4824 ,  H01L23/522 ,  H01L24/06 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

    摘要： An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.

    摘要翻译： 如本文所述的集成电路包括包括连续上部互连区域的上部互连级别，连续的上部互连区域包括多个上部接触开口。 集成电路还包括下连接级，其包括连续的下互连区域，连续的下互连区域包括多个下接触开口。 第一触点延伸穿过下接触开口到上互连区域，第二接触开口延伸穿过上接触开口到下互连区域。