公开(公告)号：US06762454B1

公开(公告)日：2004-07-13

申请号：US10118363

申请日：2002-04-08

Applicant: Effiong Ibok ,  Joong S. Jeon ,  Arvind Halliyal ,  Minh Van Ngo

Inventor： Effiong Ibok ,  Joong S. Jeon ,  Arvind Halliyal ,  Minh Van Ngo

IPC: H01L2976

CPC classification number: H01L21/28194 ,  H01L21/28044 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78 ,  H01L29/792

Abstract: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a stacked polysilicon layer formed on a dielectric layer. The stacked polysilicon layer inhibits the diffusion of boron in the dielectric layer and the penetration of boron into the dielectric layer and the semiconductor substrate.

Abstract translation: 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括形成在电介质层上的堆叠多晶硅层。 堆叠的多晶硅层抑制介电层中的硼的扩散以及硼渗透到介质层和半导体衬底中。

公开(公告)号：US06735123B1

公开(公告)日：2004-05-11

申请号：US10164895

申请日：2002-06-07

Applicant: Nicholas H. Tripsas ,  Mark T. Ramsbey ,  Wei Zheng ,  Effiong Ibok ,  Fred T K Cheung

Inventor： Nicholas H. Tripsas ,  Mark T. Ramsbey ,  Wei Zheng ,  Effiong Ibok ,  Fred T K Cheung

IPC: G11C1604

CPC classification number: H01L29/66833 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/981

Abstract: A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region between an opposing source lateral region and a drain lateral region. A control gate is positioned above the multilevel charge trapping dielectric. The multilevel charge trapping dielectric comprises a tunnel dielectric layer adjacent the substrate, a top dielectric adjacent the control gate, and a charge trapping dielectric positioned there between. The thickness of the tunnel dielectric layer in the central region is greater than a thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.

Abstract translation: 双位电介质存储单元包括具有源极区和衬底的衬底，衬底在中心沟道区的相对侧上。 多电荷电荷捕获电介质位于中心通道区域上方的衬底上，并且包括在相对的源侧向区域和漏极侧向区域之间的中心区域。 控制栅极位于多电平电荷捕获电介质的上方。 多电荷电荷俘获电介质包括邻近衬底的隧道电介质层，邻近控制栅极的顶部电介质和位于其间的电荷捕获电介质。 中心区域中的隧道介电层的厚度大于源极横向区域和漏极侧向区域中的每一个中的隧道介电层的厚度。

公开(公告)号：US06451641B1

公开(公告)日：2002-09-17

申请号：US10085348

申请日：2002-02-27

Applicant: Arvind Halliyal ,  Robert Bertram Ogle, Jr. ,  Joong S. Jeon ,  Fred Cheung ,  Effiong Ibok

Inventor： Arvind Halliyal ,  Robert Bertram Ogle, Jr. ,  Joong S. Jeon ,  Fred Cheung ,  Effiong Ibok

IPC: H01L21336

CPC classification number: H01L21/28185 ,  H01L21/2807 ,  H01L21/28194 ,  H01L29/517

Abstract: A process for fabricating a semiconductor device, including providing a semiconductor substrate; depositing on the semiconductor substrate a layer of a high-K gate dielectric material; depositing on the gate dielectric material layer a polysilicon or polysilicon-germanium gate electrode layer, in which the step of depositing the polysilicon or polysilicon-germanium gate electrode layer includes providing non-reducing conditions in a CVD apparatus.

Abstract translation: 一种制造半导体器件的方法，包括提供半导体衬底; 在半导体衬底上沉积高K栅介质材料的层; 在栅极电介质材料层上沉积多晶硅或多晶硅 - 锗栅电极层，其中沉积多晶硅或多晶硅 - 锗栅电极层的步骤包括在CVD装置中提供非还原条件。

公开(公告)号：US06207542B1

公开(公告)日：2001-03-27

申请号：US09478962

申请日：2000-01-07

Applicant: Effiong Ibok

Inventor： Effiong Ibok

IPC: H01L213205

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Nitrogen Oxide base film on a substrate, and then depositing an ultra-thin nitride film on the base film. The semiconductor device is then annealed in situ in ammonia, following which the device is oxidized in Nitrogen Oxide. FET gates are then conventionally formed over the gate insulator, and the gates are next implanted with Nitrogen to passivate dangling Nitrogen and Silicon bonds in the nitride, thus decreasing the charge content in the film. Consequently, the resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract translation: 一种用于制造包括硅衬底的半导体器件的方法，包括在衬底上形成薄氮氧化物基膜，然后在基膜上沉积超薄氮化物膜。 然后将半导体器件原位在氨中退火，随后将其置于氮氧化物中氧化。 然后通常在栅极绝缘体上形成FET栅极，然后在栅极中注入氮气以钝化氮化物中悬挂的氮和硅键，从而降低膜中的电荷含量。 因此，所得到的栅极绝缘体是电绝缘的，而不会降低相对于传统的栅极氧化物绝缘体的性能。

公开(公告)号：US6162699A

公开(公告)日：2000-12-19

申请号：US181561

申请日：1998-10-29

Applicant: Larry Wang ,  Nick Kepler ,  Olov Karlsson ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

Inventor： Larry Wang ,  Nick Kepler ,  Olov Karlsson ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  Y10S438/942 ,  Y10S438/945

Abstract: A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region. Any narrow regions are then merged together with the preliminary expanded region to produce data representing a final expanded region, which is used to produce a mask employed to produce an even width trench about the perimeter of the composite layer. The computer then generates the mask according to the results achieved and the isolation trenches are etched. The resulting isolation trenches prevent short-circuits from occurring between the various electrical devices on the semiconductor device.

Abstract translation: 用于有效地产生有限的沟槽宽度隔离结构而不会产生对凹陷问题的敏感性以产生高质量IC的方法使用计算机产生表示沟槽隔离掩模的数据，所述沟槽隔离掩模能够用于围绕有源的周边刻蚀有限的沟槽宽度隔离结构 区域层，多晶硅层和局部互连（LI）层。 一旦使用计算机上的数据来定义各个层，并且配置为使得芯片空间最大化，则使用例如逻辑OR运算符来组合边界以产生表示整个复合层的数据。 一旦确定了表示复合层的数据，则数据在所有水平方向上均匀地向外扩展预定量的λ，以产生表示初步扩展区域的数据。 然后将任何窄区域与预扩展区域合并以产生表示最终扩展区域的数据，其用于产生用于围绕复合层的周边产生均匀宽度沟槽的掩模。 然后，计算机根据实现的结果生成掩模，并且蚀刻隔离沟槽。 所产生的隔离沟槽防止在半导体器件上的各种电器件之间发生短路。

公开(公告)号：US6020238A

公开(公告)日：2000-02-01

申请号：US978107

申请日：1997-11-25

Applicant: Yue-Song He ,  Effiong Ibok

Inventor： Yue-Song He ,  Effiong Ibok

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/66825 ,  H01L21/28273

Abstract: A method of fabricating an interpolysilicon dielectric structure in a non-volatile memory includes the steps of forming a nitride layer 12 on a floating gate 10 and a high dielectric constant layer 14 on the nitride layer 12. A control gate 18 may be formed directly on the high dielectric constant layer 14, or on a thin layer 16 of an oxide or an oxynitride on the high dielectric constant layer 14.

Abstract translation: 在非易失性存储器中制造多晶硅介质结构的方法包括在氮化物层12上的浮置栅极10和高介电常数层14上形成氮化物层12的步骤。控制栅极18可直接形成在 高介电常数层14或在高介电常数层14上的氧化物或氧氮化物的薄层16上。

公开(公告)号：US5940718A

公开(公告)日：1999-08-17

申请号：US119715

申请日：1998-07-20

Applicant: Effiong Ibok ,  Yue-Song He ,  Yowjuang W. Liu

Inventor： Effiong Ibok ,  Yue-Song He ,  Yowjuang W. Liu

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76232

Abstract: A method for fabricating a semiconductor device including a silicon substrate and plural silicon stacks thereon includes forming a nitride shield layer on the substrate and stacks to cover the stacks, such that the stacks are protected from loss of critical dimension during subsequent isolation trench formation and oxidation. In other words, the edge of each stack, and thus the critical dimension of the silicon layers of the stack, is protected from oxidation by the nitride shield layer.

Abstract translation: 一种用于制造包括硅衬底和其上的多个硅堆叠的半导体器件的方法包括在衬底上形成氮化物屏蔽层并堆叠以覆盖堆叠，使得在随后的隔离沟槽形成和氧化期间保护堆叠免受临界尺寸的损失 。 换句话说，每个堆叠的边缘以及因此堆叠的硅层的临界尺寸被氮化物屏蔽层防止氧化。

公开(公告)号：US06472233B1

公开(公告)日：2002-10-29

申请号：US09586960

申请日：2000-06-05

Applicant: Khaled Z. Ahmed ,  Nguyen D. Bui ,  Effiong Ibok ,  John R. Hauser

Inventor： Khaled Z. Ahmed ,  Nguyen D. Bui ,  Effiong Ibok ,  John R. Hauser

IPC: G01R3126

CPC classification number: H01L22/34 ,  G01R31/2621 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An apparatus and method used in extracting polysilicon gate doping from C−V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.

Abstract translation: 一种用于在强反转中从C-V分析中提取多晶硅栅极掺杂的设备和方法，特别是对于超薄栅极氧化物。 对于次20埃氧化物MOS器件，沟道长度小于约10微米的晶体管并联连接，以避免强反转中的外在电容滚降。 使用端子电容的传输线模型来估计通道长度的上限，这是模拟栅隧道电流和有限通道电阻的不可忽略的因素。

公开(公告)号：US06399519B1

公开(公告)日：2002-06-04

申请号：US09479505

申请日：2000-01-07

Applicant: Effiong Ibok

Inventor： Effiong Ibok

IPC: H01L2131

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/518

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Nitrogen Oxide base film on a substrate, and then annealing the substrate in ammonia. An ultra-thin nitride film is deposited on the base film. The semiconductor device is then oxidized in Nitrogen Oxide. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract translation: 一种制造包括硅衬底的半导体器件的方法包括在衬底上形成薄氮氧化物基膜，然后用氨将衬底退火。 在基膜上沉积超薄氮化物膜。 然后将半导体器件在氮氧化物中氧化。 通常在栅极绝缘体上形成FET栅极。 所得到的栅极绝缘体是电绝缘的，而不降低相对于常规栅极氧化物绝缘体的性能。

公开(公告)号：US06380047B1

公开(公告)日：2002-04-30

申请号：US09634990

申请日：2000-08-08

Applicant: Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

Inventor： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC: H01L2176

CPC classification number: H01L21/76229

Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.

Abstract translation: 使用简化的反向源极/漏极平面化掩模，在具有改善的平面度的半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成大沟槽并用也覆盖衬底表面的绝缘材料再填充它们，掩蔽大沟槽上方的区域，蚀刻以基本上除去衬底表面上的所有绝缘材料，并抛光以平坦化绝缘材料 沟渠 然后形成围绕大沟槽的小沟槽和外围沟槽，用绝缘材料重新填充并平坦化。 由于在小沟槽之前和分开形成大沟槽，所以可以在仅在大沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 使用具有相对较大几何特征的平面化掩模的使用避免了创建和实现复杂和关键掩模的需要，从而降低制造成本并提高生产量。 此外，因为大的和小的沟槽不同时被抛光，所以避免了过度抛光，从而提高平面度，从而提高随后的光刻处理的精度。