Invention Grant
US06451641B1 Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material
有权
用于在高K栅介质材料上沉积多晶硅栅电极的非还原工艺
- Patent Title: Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material
- Patent Title (中): 用于在高K栅介质材料上沉积多晶硅栅电极的非还原工艺
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Application No.: US10085348Application Date: 2002-02-27
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Publication No.: US06451641B1Publication Date: 2002-09-17
- Inventor: Arvind Halliyal , Robert Bertram Ogle, Jr. , Joong S. Jeon , Fred Cheung , Effiong Ibok
- Applicant: Arvind Halliyal , Robert Bertram Ogle, Jr. , Joong S. Jeon , Fred Cheung , Effiong Ibok
- Main IPC: H01L21336
- IPC: H01L21336
Abstract:
A process for fabricating a semiconductor device, including providing a semiconductor substrate; depositing on the semiconductor substrate a layer of a high-K gate dielectric material; depositing on the gate dielectric material layer a polysilicon or polysilicon-germanium gate electrode layer, in which the step of depositing the polysilicon or polysilicon-germanium gate electrode layer includes providing non-reducing conditions in a CVD apparatus.
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