公开(公告)号：US5939763A

公开(公告)日：1999-08-17

申请号：US708428

申请日：1996-09-05

Applicant: Ming-Yin Hao ,  Robert Bertram Ogle, Jr. ,  Derick Wristers

Inventor： Ming-Yin Hao ,  Robert Bertram Ogle, Jr. ,  Derick Wristers

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/318 ,  H01L27/115 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Abstract translation: 描述了用于生长用作MOSFET栅极氧化物或用于EEPROM的隧道氧化物的超薄介电层的工艺。 通过一氧化氮和一氧化二氮气体中的一系列退火形成氮氧化物层，其在晶圆 - 氧氮化物界面处和氧氮化物表面处的氮浓度具有峰值，并且在氮氧化物本体中具有低氮浓度。 该方法提供精确的厚度控制，改进的界面结构，电子陷阱的低密度，并阻止从介质和衬底扩散掺杂剂杂质。 该过程很容易集成到现有的制造过程中，并且增加了很少的成本。

公开(公告)号：US20080149986A1

公开(公告)日：2008-06-26

申请号：US11614801

申请日：2006-12-21

Applicant: Robert Bertram Ogle, Jr. ,  Joong Jeon ,  Austin Frenkel ,  Eric Paton

Inventor： Robert Bertram Ogle, Jr. ,  Joong Jeon ,  Austin Frenkel ,  Eric Paton

IPC: H01L21/4763 ,  H01L29/788 ,  B05C11/02

CPC classification number: H01L21/28273 ,  H01L21/02068 ,  H01L27/11526 ,  H01L27/11531

Abstract: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.

Abstract translation: 公开了一种用于处理闪存器件的零氧化物界面双重多晶硅结构的系统和方法。 示例性的方法可以包括去除第一多晶硅层的表面上的氧化物并在同一处理室中在第一多晶硅层上形成第二多晶硅层。 不需要从氧化物去除工具到例如多层形成工具，植入工具等的结构的转移。 结果，在第一和第二多层的界面处不形成含有由第一多晶硅层暴露于含氧气氛的氧化硅的杂质。

公开(公告)号：US06451641B1

公开(公告)日：2002-09-17

申请号：US10085348

申请日：2002-02-27

Applicant: Arvind Halliyal ,  Robert Bertram Ogle, Jr. ,  Joong S. Jeon ,  Fred Cheung ,  Effiong Ibok

Inventor： Arvind Halliyal ,  Robert Bertram Ogle, Jr. ,  Joong S. Jeon ,  Fred Cheung ,  Effiong Ibok

IPC: H01L21336

CPC classification number: H01L21/28185 ,  H01L21/2807 ,  H01L21/28194 ,  H01L29/517

Abstract: A process for fabricating a semiconductor device, including providing a semiconductor substrate; depositing on the semiconductor substrate a layer of a high-K gate dielectric material; depositing on the gate dielectric material layer a polysilicon or polysilicon-germanium gate electrode layer, in which the step of depositing the polysilicon or polysilicon-germanium gate electrode layer includes providing non-reducing conditions in a CVD apparatus.

Abstract translation: 一种制造半导体器件的方法，包括提供半导体衬底; 在半导体衬底上沉积高K栅介质材料的层; 在栅极电介质材料层上沉积多晶硅或多晶硅 - 锗栅电极层，其中沉积多晶硅或多晶硅 - 锗栅电极层的步骤包括在CVD装置中提供非还原条件。

公开(公告)号：US06709927B1

公开(公告)日：2004-03-23

申请号：US09927134

申请日：2001-08-10

Applicant: Robert Bertram Ogle, Jr. ,  Arvind Halliyal

Inventor： Robert Bertram Ogle, Jr. ,  Arvind Halliyal

IPC: H01L21336

CPC classification number: H01L21/28185 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31612 ,  H01L29/512 ,  H01L29/518 ,  H01L29/7881

Abstract: A process to deposit a silicon dioxide layer on a silicon nitride layer for an ONO stack of a floating gate transistor. Silicon dioxide is deposited on a silicon nitride layer and annealed in a batch furnace or a single wafer rapid thermal anneal tool in a nitrogen oxide (NO) or nitrous oxide (N2O) ambient environment.

Abstract translation: 一种在浮栅晶体管的ONO堆叠的氮化硅层上沉积二氧化硅层的工艺。 二氧化硅沉积在氮化硅层上，并在氮化氧（NO）或一氧化二氮（N2O））环境环境中的分批炉或单晶片快速热退火工具中进行退火。

公开(公告)号：US08803216B2

公开(公告)日：2014-08-12

申请号：US11277008

申请日：2006-03-20

Applicant: Meng Ding ,  Lei Xue ,  Mark Randolph ,  Chi Chang ,  Robert Bertram Ogle, Jr.

Inventor： Meng Ding ,  Lei Xue ,  Mark Randolph ,  Chi Chang ,  Robert Bertram Ogle, Jr.

IPC: H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/7923

Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Abstract translation: 一种存储单元系统，包括提供衬底，在衬底上形成具有富含硅的氮化物的电荷存储堆叠，并在电荷存储堆上形成栅极。

公开(公告)号：US06245689B1

公开(公告)日：2001-06-12

申请号：US09252854

申请日：1998-09-08

Applicant: Ming-Yin Hao ,  Robert Bertram Ogle, Jr. ,  Derick Wristers

Inventor： Ming-Yin Hao ,  Robert Bertram Ogle, Jr. ,  Derick Wristers

IPC: H01L2131

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: A process for growing an ultra-thin dielelctric layer for use as a MOSFET gate or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density electron traps, and impedes dopant impurity diffusion from/to the dielelctric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Abstract translation: 描述了用于生长用作MOSFET栅极的超薄晶体管层或用于EEPROM的隧道氧化物的工艺。 通过一氧化氮和一氧化二氮气体中的一系列退火形成氮氧化物层，其在晶圆 - 氧氮化物界面处和氧氮化物表面处的氮浓度具有峰值，并且在氮氧化物本体中具有低氮浓度。 该工艺提供精确的厚度控制，改进的界面结构，低密度电子陷阱，并阻止掺杂剂杂质扩散到离子和底物。 该过程很容易集成到现有的制造过程中，并且增加了很少的成本。