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6 条记录 (耗时 0.053 秒)

    Low cost shallow trench isolation using non-conformal dielectric material
    1.
    发明授权
    Low cost shallow trench isolation using non-conformal dielectric material 失效
    使用非保形介质材料的低成本浅沟槽隔离

    公开(公告)号：US06270353B1

    公开(公告)日：2001-08-07

    申请号：US09326925

    申请日：1999-06-07

    申请人： John W. Andrews ,  Bao T. Hwang ,  Howard S. Landis ,  Shaw-Ning Mei ,  James M. Tyler ,  Edward J. Vishnesky

    发明人： John W. Andrews ,  Bao T. Hwang ,  Howard S. Landis ,  Shaw-Ning Mei ,  James M. Tyler ,  Edward J. Vishnesky

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229

    摘要： A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

    摘要翻译： 提供了一种用于平坦化诸如半导体衬底上的浅沟槽隔离区域的结构的方法。 设置有具有基本垂直和水平表面的升高和降低区域的半导体衬底。 降低的区域可以对应于沟槽区域。 诸如非保形高密度等离子体氧化物的填充材料可以在水平表面上沉积至至少等于预定高度的厚度，以便提供填充材料的升高和降低的区域。 然后可以选择性地去除填充材料的凸起区域，而不去除降低区域中的填充材料。

    Method to planarize semiconductor surface
    2.
    发明授权
    Method to planarize semiconductor surface 失效
    平面化半导体表面的方法

    公开(公告)号：US06531265B2

    公开(公告)日：2003-03-11

    申请号：US09737240

    申请日：2000-12-14

    申请人： Shaw-Ning Mei ,  T. Howard Shillingford ,  Edward J. Vishnesky

    发明人： Shaw-Ning Mei ,  T. Howard Shillingford ,  Edward J. Vishnesky

    IPC分类号： G03F736

    CPC分类号： H01L21/76229 ,  G03F7/0035 ,  H01L21/31053

    摘要： A method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process is described. Shallow recesses on a semiconductor surface are filled with a filling material. The filling material is deposited on the semiconductor surface to a thickness approximately equal to the depth of the shallow recesses. A selectively etchable material is formed on the filling material. A reverse mask (RM) is used to pattern the selectively etchable material to form segments of the selectively etchable material equal to the pattern of the shallow recesses and aligned to the shallow recesses. Exposed filling material is removed followed by the removal of the segments of the selectively etchable material. The remaining filling material in the shallow recesses forms fences which extend above the surface of the semiconductor. The fences are removed resulting in a planar semiconductor surface.

    摘要翻译： 描述了使用栅栏创建和消除（FCE）工艺对半导体表面进行平面化的方法。 在半导体表面上的浅凹部填充有填充材料。 填充材料沉积在半导体表面上至大约等于浅凹槽深度的厚度。 在填充材料上形成可选择的可蚀刻材料。 反向掩模（RM）用于对可选择的可蚀刻材料进行图案以形成等于浅凹槽的图案并与浅凹槽对准的可选择性蚀刻材料的段。 去除曝光的填充材料，然后移除可选择性蚀刻材料的段。 浅凹槽中的剩余填充材料形成在半导体表面之上延伸的栅栏。 去除栅栏，导致平面半导体表面。

    Shallow trench isolation using non-conformal dielectric and planarizatrion
    4.
    发明授权
    Shallow trench isolation using non-conformal dielectric and planarizatrion 有权
    使用非保形介质和平面化的浅沟槽隔离

    公开(公告)号：US06541349B2

    公开(公告)日：2003-04-01

    申请号：US09764674

    申请日：2001-01-18

    申请人： Senthilkumar Arthanari ,  Shaw-Ning Mei ,  Edward J. Vishnesky

    发明人： Senthilkumar Arthanari ,  Shaw-Ning Mei ,  Edward J. Vishnesky

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229

    摘要： A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.

    摘要翻译： 提供了一种用于平坦化诸如半导体衬底上的浅沟槽隔离区域的结构的方法。 设置有具有基本垂直和水平表面的升高和降低区域的半导体衬底。 降低的区域可以对应于沟槽区域。 上部区域由具有预定厚度的氮化物掩蔽层覆盖。 诸如非保形高密度等离子体氧化物的填充材料可以沉积在水平表面上，其厚度终止于氮化物层厚度的厚度。 然后在单个平面化步骤中选择性地除去填充材料的凸起区域，而不用磨料浆料使用固定的研磨硬质抛光垫去除降低区域中的填料。

    Flash memory structure with floating gate in vertical trench
    5.
    发明授权
    Flash memory structure with floating gate in vertical trench 有权
    闪存结构，浮动栅极在垂直沟槽中

    公开(公告)号：US6130453A

    公开(公告)日：2000-10-10

    申请号：US225055

    申请日：1999-01-04

    申请人： Shaw-Ning Mei ,  Edward J. Vishnesky

    发明人： Shaw-Ning Mei ,  Edward J. Vishnesky

    IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L29/42336 ,  H01L27/11293 ,  H01L29/66825 ,  H01L29/7885

    摘要： A flash memory cell comprises a substrate having a trench formed below the substrate surface, a vertical bit line or auxiliary gate deposited in the trench below the surface, a drain region formed in the substrate below the bit line, and a split floating gate deposited in the trench below the surface to a depth less than the vertical bit line. The floating gate includes a first vertical portion on one side of the bit line and a second vertical portion on another side of the bit line opposite the first vertical portion, with each portion of the gate being accessed by the bit line. The memory cell further includes a source region formed below the surface spaced apart from and adjacent each of the floating gate portions and a word line or control gate extending over the substrate, bit line and floating gate portions. The vertical bit line and split floating gate portions extend from the substrate surface to the bottom of the trench, and adjacent portions of the bit line and the floating gate portions extend above the substrate surface at substantially the same height.

    摘要翻译： 闪存单元包括具有形成在衬底表面下方的沟槽的衬底，沉积在表面下方的沟槽中的垂直位线或辅助栅极，形成在位线下方的衬底中的漏极区域和沉积在 表面下方的沟槽深度小于垂直位线。 浮动栅极包括在位线的一侧上的第一垂直部分和位于与第一垂直部分相对的位线的另一侧上的第二垂直部分，栅极的每个部分被位线访问。 存储单元还包括形成在与每个浮动栅极部分间隔开并相邻的表面下方的源极区域，以及在衬底，位线和浮动栅极部分上延伸的字线或控制栅极。 垂直位线和分离的浮动栅极部分从衬底表面延伸到沟槽的底部，并且位线和浮动栅极部分的相邻部分在基本相同的高度处在衬底表面上方延伸。