公开(公告)号：US09164769B2

公开(公告)日：2015-10-20

申请号：US12962741

申请日：2010-12-08

Applicant: Won-Sub Kim ,  Tai-Song Jin ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Jin-Seok Lee

Inventor： Won-Sub Kim ,  Tai-Song Jin ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Jin-Seok Lee

IPC: G06F9/318 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30189 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/3887 ,  G06F9/3889

Abstract: A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files.

Abstract translation: 提供可重构阵列。 可重配置阵列包括超长指令字（VLIW）模式和粗粒子阵列（CGA）模式。 当VLIW模式转换为CGA模式时，不是在VLIW模式和CGA模式之间共享中央寄存器文件，而是将CGA模式中使用的实时数据从中央寄存器文件复制到本地寄存器文件。

公开(公告)号：US09015451B2

公开(公告)日：2015-04-21

申请号：US12048658

申请日：2008-03-14

Applicant: Il Hyun Park ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Dong Kwan Suh ,  Jeongwook Kim ,  Choon Ki Jang

Inventor： Il Hyun Park ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Dong Kwan Suh ,  Jeongwook Kim ,  Choon Ki Jang

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F9/3824 ,  G06F9/383 ,  G06F9/3885

Abstract: A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.

Abstract translation: 提供了处理器和存储器管理方法。 处理器包括处理器核心，经由单个端口向处理器核心传送数据的高速缓冲存储器，并存储由处理器核心访问的数据，以及将数据传送到处理器或从处理器收发的暂存器存储器（SPM） 核心经由多个多端口中的至少一个。

公开(公告)号：US08793437B2

公开(公告)日：2014-07-29

申请号：US11835635

申请日：2007-08-08

Applicant: Jong Myon Kim ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Dong Kwan Suh ,  Jeongwook Kim

Inventor： Jong Myon Kim ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Dong Kwan Suh ,  Jeongwook Kim

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0897 ,  G06F12/123

Abstract: A cache memory system using temporal locality information and a data storage method are provided. The cache memory system including: a main cache which stores data accessed by a central processing unit; an extended cache which stores the data if the data is evicted from the main cache; and a separation cache which stores the data of the extended cache when the data of the extended cache is evicted from the extended cache and temporal locality information corresponding to the data of the extended cache satisfies a predetermined condition.

Abstract translation: 提供了一种使用时间局部性信息和数据存储方法的缓存存储器系统。 高速缓冲存储器系统包括：主缓存器，其存储由中央处理单元访问的数据; 如果数据从主缓存中逐出，则存储数据的扩展高速缓存; 以及分离高速缓存，当扩展高速缓冲存储器的数据从扩展高速缓存中逐出时存储扩展高速缓存的数据，并且与扩展高速缓冲存储器的数据相对应的时间位置信息满足预定条件。

公开(公告)号：US08555097B2

公开(公告)日：2013-10-08

申请号：US12609920

申请日：2009-10-30

Applicant: Bernhard Egger ,  Soo-jung Ryu ,  Dong-hoon Yoo

Inventor： Bernhard Egger ,  Soo-jung Ryu ,  Dong-hoon Yoo

IPC: G06F1/32

CPC classification number: G06F9/30076 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/38 ,  G06F9/3897 ,  G06F15/7867 ,  Y02D10/126 ,  Y02D10/14

Abstract: Described herein is a reconfigurable processor which uses a distributed configuration memory structure and an operation method thereof in which power consumption is reduced. A processing unit which configures the reconfigurable processor includes a functional unit, a distributed configuration memory, a no-operation (NOP) register, and a controller. The NOP register stores information which represents whether or not a NOP operation is performed at each clock cycle. The controller controls to deactivate the distributed configuration memory at a clock cycle at which a NOP operation is performed.

Abstract translation: 这里描述的是使用其中功耗降低的分布式配置存储器结构及其操作方法的可重构处理器。 配置可重构处理器的处理单元包括功能单元，分布式配置存储器，无操作（NOP）寄存器和控制器。 NOP寄存器存储表示在每个时钟周期是否执行NOP操作的信息。 控制器控制在执行NOP操作的时钟周期停用分布式配置存储器。

公开(公告)号：US20120185675A1

公开(公告)日：2012-07-19

申请号：US13177823

申请日：2011-07-07

Applicant: Jae-Young KIM ,  Dong-Hoon Yoo ,  Yeon-Gon Cho ,  Hee-Jun Shim ,  Chang-Moo Kim

Inventor： Jae-Young KIM ,  Dong-Hoon Yoo ,  Yeon-Gon Cho ,  Hee-Jun Shim ,  Chang-Moo Kim

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30189 ,  G06F9/30072 ,  G06F11/3636

Abstract: An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid trace data.

Abstract translation: 提供了一种用于压缩跟踪数据的装置和方法。 该装置包括：检测单元，被配置为检测对应于在可重配置处理器中执行基本上显着的操作的一个或多个功能单元的跟踪数据作为有效跟踪数据;以及压缩单元，被配置为压缩有效跟踪数据。

公开(公告)号：US20120144399A1

公开(公告)日：2012-06-07

申请号：US13217498

申请日：2011-08-25

Applicant: Won Sub KIM ,  Bernhard EGGER ,  Dong-Hoon YOO ,  Jin-Seok LEE ,  Taisong JIN

Inventor： Won Sub KIM ,  Bernhard EGGER ,  Dong-Hoon YOO ,  Jin-Seok LEE ,  Taisong JIN

IPC: G06F9/46

CPC classification number: G06F9/544

Abstract: A method and apparatus for thread synchronization is provided. The apparatus for thread synchronization includes a reader configured to generate a data read request, a writer configured to generate a data write request, a register file configured to have a full status indicating that the register file stores data and an empty status indicating that the register file stores no data, and a controller configured to receive the data read request from the reader or the data write request from the writer, and to process the received data read request or the received data write request while stalling or releasing the reader or the writer according to whether the register file is in the full status or in the empty status and according to an operating status of the reader or the writer.

Abstract translation: 提供了一种用于线程同步的方法和装置。 用于线程同步的装置包括被配置为产生数据读取请求的读取器，被配置为生成数据写入请求的写入器，被配置为具有指示该寄存器文件存储数据的完整状态的寄存器文件以及指示该寄存器 文件不存储数据，并且控制器被配置为从读取器接收数据读取请求或来自写入器的数据写入请求，并且在停止或释放读取器或写入器的同时处理接收的数据读取请求或接收的数据写入请求 根据注册文件是处于完整状态还是处于空状态，并根据读写器的操作状态。

公开(公告)号：US20120124351A1

公开(公告)日：2012-05-17

申请号：US13217952

申请日：2011-08-25

Applicant: Bernhard Egger ,  Dong-Hoon Yoo ,  Tai-Song Jin ,  Won-Sub Kim ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Hee-Jin Ahn

Inventor： Bernhard Egger ,  Dong-Hoon Yoo ,  Tai-Song Jin ,  Won-Sub Kim ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Hee-Jin Ahn

IPC: G06F9/38

CPC classification number: G06F15/7867 ,  G06F8/452 ,  G06F9/38 ,  G06F9/3853 ,  G06F9/3897 ,  G06F11/3409

Abstract: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.

Abstract translation: 提供了用于动态地确定可重构阵列的执行模式的装置和方法。 可以在循环执行之前和/或期间获得循环的性能信息。 性能信息可用于确定是否以非常长的指令字（VLIW）模式或粗粒度阵列（CGA）模式操作装置。

公开(公告)号：US20120054468A1

公开(公告)日：2012-03-01

申请号：US13216852

申请日：2011-08-24

Applicant: Bernhard EGGER ,  Dong-Hoon YOO

Inventor： Bernhard EGGER ,  Dong-Hoon YOO

IPC: G06F9/318 ,  G06F9/02 ,  G06F15/80

CPC classification number: G06F9/3877 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3836 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0886 ,  G06F12/0893 ,  G06F2212/601 ,  Y02D10/13

Abstract: An apparatus and method that includes a single memory as a VLIW instruction cache and CGA configuration memory is provided. Data is provided from a storage unit to a processing core that is capable of processing data in a first mode and a second mode. If the processing core is processing in the first mode, first data is output. If the processing core is processing in the second mode, second data is output.

Abstract translation: 提供了包括作为VLIW指令高速缓存和CGA配置存储器的单个存储器的装置和方法。 从存储单元向能够处理第一模式和第二模式的数据的处理核提供数据。 如果处理核心在第一模式下处理，则输出第一数据。 如果处理核心在第二模式中处理，则输出第二数据。

公开(公告)号：US20110202749A1

公开(公告)日：2011-08-18

申请号：US12912533

申请日：2010-10-26

Applicant: Tai-Song Jin ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Won-Sub Kim ,  Jin-Seok Lee ,  Sun-Hwa Kim ,  Hee-Jin Ahn

Inventor： Tai-Song Jin ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Won-Sub Kim ,  Jin-Seok Lee ,  Sun-Hwa Kim ,  Hee-Jin Ahn

IPC: G06F9/318

CPC classification number: G06F9/3822 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/3853

Abstract: An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.

Abstract translation: 提供了一种用于并行处理计算机例如非常长的指令字（VLIW）计算机的指令压缩装置和方法。 指令压缩装置包括束代码生成单元，指令压缩单元和指令转换单元。 捆绑代码生成单元可以响应于要压缩的指令的输入而生成捆绑代码。 捆绑码可以指示当前指令组是否终止，以及当前指令组之后的指令组是否是无操作（NOP）指令组。 指令压缩单元可以根据所生成的包代码从输入指令中去除NOP指令和/或NOP指令组。 指令转换单元可以包括尚未被指令压缩单元去除的剩余指令中的生成的捆绑代码。

公开(公告)号：US20100211759A1

公开(公告)日：2010-08-19

申请号：US12706006

申请日：2010-02-16

Applicant: Bernhard Egger ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  II-hyun Park

Inventor： Bernhard Egger ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  II-hyun Park

IPC: G06F15/76 ,  G06F9/02 ,  G06F9/312

CPC classification number: G06F15/82 ,  G06F9/30072 ,  G06F9/3853

Abstract: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.

Abstract translation: 本文提供了一种用于生成支持预定执行的非常长的指令字（VLIW）命令和用于处理VLIW的VLIW处理器和方法的装置和方法。 VLIW命令包括由并行执行的多个指令形成的指令束和指示预测执行的单个值，并且使用用于生成VLIW命令的装置和方法生成。 根据指示预先执行的值，VLIW处理器并行地解码指令束并且并行地执行包括在解码指令束中的指令。