公开(公告)号：US20090166681A1

公开(公告)日：2009-07-02

申请号：US11968552

申请日：2008-01-02

Applicant: Marc Tiebout ,  Daniel Kehrer ,  Domagoj Siprak ,  Pierre Mayr ,  Johannes Kunze ,  Christopher Weyers

Inventor： Marc Tiebout ,  Daniel Kehrer ,  Domagoj Siprak ,  Pierre Mayr ,  Johannes Kunze ,  Christopher Weyers

IPC: H01L29/78

CPC classification number: H01L23/5283 ,  H01L23/4824 ,  H01L23/528 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/30105 ,  H01L2924/00

Abstract: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

Abstract translation: 根据本发明的一个实施例，MOS晶体管包括半导体层，其包括源极区，漏极区和设置在源极区和漏极区之间的沟道区。 栅极结构布置在沟道区域的上方。 源极布线结构布置在源极区域的上方并与源极区域连接。 漏极布线结构布置在漏极区上方并连接到漏极区。 源极布线结构的宽度大于漏极布线结构的宽度，源极布线结构的高度小于漏极布线结构的高度，反之亦然。

公开(公告)号：US20070146948A1

公开(公告)日：2007-06-28

申请号：US11431930

申请日：2006-05-10

Applicant: Daniel Kehrer ,  Hans-Dieter Wohlmuth

Inventor： Daniel Kehrer ,  Hans-Dieter Wohlmuth

IPC: H02H9/00

CPC classification number: H03K17/005 ,  H03K3/356043 ,  H03K17/691 ,  H03K17/693

Abstract: An integrated multiplexer circuit arrangement and an integrated latch circuit arrangement is disclosed. In one embodiment, a transformer is set up and connected up in such a way that it electrically decouples a data signal circuit and a clock signal circuit, and that it makes a clock signal of the clock signal circuit available as a control signal for the data signal circuit. The transformer includes two secondary-side end terminals directly coupled to the data signal circuit and a secondary-side center terminal coupled to a bias current source.

Abstract translation: 公开了集成多路复用器电路装置和集成锁存电路装置。 在一个实施例中，变压器被建立并连接起来，使得它使数据信号电路和时钟信号电路电耦合，并且使得时钟信号电路的时钟信号可用作数据的控制信号 信号电路。 变压器包括直接耦合到数据信号电路的两个次级侧端子端子和耦合到偏置电流源的次级侧中心端子。

公开(公告)号：US20130154868A1

公开(公告)日：2013-06-20

申请号：US13325935

申请日：2011-12-14

Applicant: Daniel Kehrer ,  Kai Jung

Inventor： Daniel Kehrer ,  Kai Jung

IPC: G01S7/36

CPC classification number: H04B1/1036 ,  H03H7/0115 ,  H03H7/1758 ,  H03H7/1766 ,  H04B1/109 ,  H04B1/18

Abstract: In accordance with an embodiment, a radio-frequency (RF) front-end for a radio configured to receive an RF signal at a first frequency includes an antenna port configured to be coupled to an antenna, and a notch filter having an input coupled to the antenna port. The notch filter is configured to reject one or more frequencies, such that the first frequency is a harmonic or intermodulation distortion product of the one or more frequencies. The RF front-end also includes a piezoelectric filter having an input coupled to an output of the notch filter and an output configured to be coupled to an RF amplifier. The piezoelectric filter has a pass band comprising the first frequency.

Abstract translation: 根据实施例，被配置为以第一频率接收RF信号的无线电的射频（RF）前端包括被配置为耦合到天线的天线端口和陷波滤波器，其具有耦合到 天线端口。 陷波滤波器被配置为拒绝一个或多个频率，使得第一频率是一个或多个频率的谐波或互调失真积。 RF前端还包括压电滤波器，其具有耦合到陷波滤波器的输出的输入和被配置为耦合到RF放大器的输出。 压电滤波器具有包括第一频率的通带。

公开(公告)号：US20090219063A1

公开(公告)日：2009-09-03

申请号：US12040473

申请日：2008-02-29

Applicant: Daniel Kehrer ,  Hermann Ruckerbauer ,  Martin Streibl

Inventor： Daniel Kehrer ,  Hermann Ruckerbauer ,  Martin Streibl

IPC: H03B19/00

CPC classification number: G06F1/10 ,  H03K23/40

Abstract: Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

Abstract translation: 本发明的实施例涉及一种集成电路，其包括被配置为以第一时钟频率操作的至少一个功能单元。 集成电路还包括源自接触焊盘的至少一个第一互连件，并且通向至少一个分频器，该至少一个分频器配置成接收具有第二频率的时钟信号，并产生一个或多个时钟信号以在第一频率下操作功能单元。 集成电路还包括耦合分频器的输出和功能单元的输入的至少一个第二互连，其中第二有线互连的总长度小于第一有线互连的总长度。

公开(公告)号：US07956665B2

公开(公告)日：2011-06-07

申请号：US12040473

申请日：2008-02-29

Applicant: Daniel Kehrer ,  Hermann Ruckerbauer ,  Martin Streibl

Inventor： Daniel Kehrer ,  Hermann Ruckerbauer ,  Martin Streibl

IPC: H03K3/00

CPC classification number: G06F1/10 ,  H03K23/40

Abstract: Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

Abstract translation: 本发明的实施例涉及一种集成电路，其包括被配置为以第一时钟频率操作的至少一个功能单元。 集成电路还包括源自接触焊盘的至少一个第一互连件，并且通向至少一个分频器，该至少一个分频器配置成接收具有第二频率的时钟信号，并产生一个或多个时钟信号以在第一频率下操作功能单元。 集成电路还包括耦合分频器的输出和功能单元的输入的至少一个第二互连，其中第二有线互连的总长度小于第一有线互连的总长度。

公开(公告)号：US20070286271A1

公开(公告)日：2007-12-13

申请号：US11760450

申请日：2007-06-08

Applicant: Daniel Kehrer ,  Franz Weiss

Inventor： Daniel Kehrer ,  Franz Weiss

IPC: H03H7/30

CPC classification number: H03H17/0219 ,  H03H15/00 ,  H03H17/0294 ,  H03H17/06 ,  H03H2017/0245

Abstract: An integrated circuit having a filter apparatus for filtering a first symbol sequence is disclosed. The first symbol sequence has a predetermined symbol duration. The apparatus includes at least one delay device which is clocked in accordance with a clock, and configured to delay the first symbol sequence by a delay time. A relationship between the delay time of the delay device and a clock duration of the clocked delay device has a predetermined value which is not equal to the one.

Abstract translation: 公开了一种具有用于滤波第一符号序列的滤波器装置的集成电路。 第一符号序列具有预定的符号持续时间。 该装置包括至少一个根据时钟计时并延迟第一符号序列延迟时间的延迟装置。 延迟装置的延迟时间与时钟延迟装置的时钟持续时间之间的关系具有不等于预定值的预定值。

公开(公告)号：US20060232349A1

公开(公告)日：2006-10-19

申请号：US10520805

申请日：2003-07-11

Applicant: Daniel Kehrer ,  Herbert Knapp

Inventor： Daniel Kehrer ,  Herbert Knapp

IPC: G01D5/20

CPC classification number: H03F3/45183 ,  H01L2924/0002 ,  H03F2203/45562 ,  H03F2203/45638 ,  H03H7/0115 ,  H01L2924/00

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes an output circuit having at least one first output connection which can provide a data signal, at least one first data output connection; and at least one first inductance connected between the at least one first output connection and the at least one data output connection.

公开(公告)号：US20120299170A1

公开(公告)日：2012-11-29

申请号：US13116285

申请日：2011-05-26

Applicant: Daniel Kehrer ,  Stefan Martens ,  Tze Yang Hin ,  Helmut Wietschorke ,  Horst Theuss ,  Beng Keh See ,  Ulrich Krumbein

Inventor： Daniel Kehrer ,  Stefan Martens ,  Tze Yang Hin ,  Helmut Wietschorke ,  Horst Theuss ,  Beng Keh See ,  Ulrich Krumbein

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/495 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/16 ,  H01L2223/6611 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module comprises a first semiconductor device, a frame arranged on the first semiconductor device, the frame comprising a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Abstract translation: 公开了一种用于制造模块的模块和方法。 模块的实施例包括第一半导体器件，布置在第一半导体器件上的框架，框架包括空腔，以及布置在框架上的第二半导体器件，其中第二半导体器件密封空腔。

公开(公告)号：US08189726B2

公开(公告)日：2012-05-29

申请号：US12042599

申请日：2008-03-05

Applicant: Franz Weiss ,  Daniel Kehrer

Inventor： Franz Weiss ,  Daniel Kehrer

IPC: H04L7/00 ,  H04L12/26 ,  G01R31/28

CPC classification number: H04J3/047 ,  H04J3/0685

Abstract: Embodiments of the invention relate to integrated circuits comprising inputs for receiving an input signal and a plurality of clock signals having a predetermined phase relationship. The integrated circuit may include a plurality of track-and-hold devices and a plurality of slicer devices. Signal outputs of two track-and-hold devices may be coupled to signal inputs of one slicer device, one of the two track-and-hold devices and the slicer device being coupled to a first input configured to receive a first clock signal and the other track-and-hold device being coupled to a second input being configured to receive a second clock signal.

Abstract translation: 本发明的实施例涉及包括用于接收输入信号和具有预定相位关系的多个时钟信号的输入的集成电路。 集成电路可以包括多个跟踪和保持设备以及多个限幅器设备。 两个跟踪和保持设备的信号输出可以耦合到一个限幅器设备的信号输入，两个跟踪和保持设备中的一个和限幅器设备被耦合到被配置为接收第一时钟信号的第一输入端，并且 耦合到第二输入的其它跟踪和保持设备被配置为接收第二时钟信号。

公开(公告)号：US07977709B2

公开(公告)日：2011-07-12

申请号：US11968552

申请日：2008-01-02

Applicant: Marc Tiebout ,  Daniel Kehrer ,  Domagoj Siprak ,  Pierre Mayr ,  Johannes Kunze ,  Christopher Weyers

Inventor： Marc Tiebout ,  Daniel Kehrer ,  Domagoj Siprak ,  Pierre Mayr ,  Johannes Kunze ,  Christopher Weyers

IPC: H01L27/18

CPC classification number: H01L23/5283 ,  H01L23/4824 ,  H01L23/528 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/30105 ,  H01L2924/00

Abstract: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

Abstract translation: 根据本发明的一个实施例，MOS晶体管包括半导体层，其包括源极区，漏极区和设置在源极区和漏极区之间的沟道区。 栅极结构布置在沟道区域的上方。 源极布线结构布置在源极区域的上方并与源极区域连接。 漏极布线结构布置在漏极区上方并连接到漏极区。 源极布线结构的宽度大于漏极布线结构的宽度，源极布线结构的高度小于漏极布线结构的高度，反之亦然。