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    INTEGRATED NUCLEIC ACID TEST SYSTEM, INSTRUMENT AND METHOD
    1.
    发明申请
    INTEGRATED NUCLEIC ACID TEST SYSTEM, INSTRUMENT AND METHOD 有权

    公开(公告)号：US20220195355A1

    公开(公告)日：2022-06-23

    申请号：US17576087

    申请日：2022-01-14

    Applicant: DNAe Group Holdings Limited

    Inventor： Christofer TOUMAZOU ,  David DAVIDSON ,  Samuel REED

    IPC: C12M1/34 ,  B01L3/00 ,  C12Q1/6874 ,  C12M1/36 ,  C12Q1/6825 ,  C12Q1/6844

    Abstract: A method of analysing nucleic acid using apparatus comprising a reaction chamber and plurality of sensors located in the base of the chamber, with each sensor preferably located within a respective well. The method comprises flowing a fluid containing the nucleic acid or fragments thereof into the reaction chamber. While the chamber is fully or at least partially sealed, amplification of the nucleic acid or said fragments is performed within the chamber using an amplification primer or primers whilst detecting the generation of amplicons using said sensors. Sequencing or hybridisation is then performed on the amplicons, and sequencing or hybridisation is detected using said sensors.

    Electrostatic discharge protection
    6.
    发明授权
    Electrostatic discharge protection 有权
    静电放电保护

    公开(公告)号：US09431387B2

    公开(公告)日：2016-08-30

    申请号：US14937847

    申请日：2015-11-10

    Applicant: DNAE GROUP HOLDINGS LIMITED

    Inventor： David Garner ,  Hua Bai

    IPC: H01L27/02 ,  H01L29/66 ,  G01N27/414

    CPC classification number: H01L27/0251 ,  G01N27/4148 ,  H01L27/0288 ,  H01L27/0292 ,  H01L29/66825

    Abstract: A device comprising an electrostatic discharge protection structure, an ion sensitive field effect transistor (ISFET) having a floating gate, and a sensing layer located above the floating gate. The device is configured such that the electrical impedance from the sensing layer to the electrostatic discharge protection structure is less than the electrical impedance from the sensing layer to the floating gate. The device can be fabricated in a standard CMOS process.

    Abstract translation: 一种包括静电放电保护结构的装置，具有浮置栅极的离子敏感场效应晶体管（ISFET）和位于浮置栅极上方的感测层。 该器件被配置为使得从感测层到静电放电保护结构的电阻抗小于从感测层到浮动栅极的电阻抗。 该器件可以用标准CMOS工艺制造。

    IMPROVEMENTS IN OR RELATING TO PACKAGING FOR INTEGRATED CIRCUITS
    9.
    发明申请
    IMPROVEMENTS IN OR RELATING TO PACKAGING FOR INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20190302051A1

    公开(公告)日：2019-10-03

    申请号：US16302359

    申请日：2017-05-15

    Applicant: DNAe Group Holdings Limited

    Inventor： Zahid Ansari

    IPC: G01N27/414 ,  H01L23/31 ,  H01L27/088

    Abstract: An assay device (10) is provided. The device comprises an integrated circuit (IC) (16) comprising a plurality of ISFETs (18); an over-moulded layer (17) which partially covers the IC, such that the plurality of ISFETs remain uncovered; and a film (20) provided across substantially the entire IC. The film acts as a passivation and/or sensing layer for each of the ISFETs. In addition, the film acts as a barrier layer to encase the over-moulded layer.

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