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    Mitigating instruction prediction latency with independently filtered presence predictors
    3.
    发明授权
    Mitigating instruction prediction latency with independently filtered presence predictors 有权
    用独立过滤的存在预测器缓解指令预测延迟

    公开(公告)号：US09152424B2

    公开(公告)日：2015-10-06

    申请号：US13523784

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/38 ,  G06F9/3806 ,  G06F9/3848

    摘要： Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.

    摘要翻译： 本公开的实施例包括使用耦合到处理器管线的独立滤波的指令预测存在预测器来减轻指令预测等待时间。 预测存在预测器包括多个存在预测器，其被配置为并行地接收指令地址并且生成相关联的指令预测的未过滤的指示。 预测存在预测器包括多个动态滤波器，每个动态滤波器耦合到多个存在预测器之一。 每个动态过滤器被配置为基于其耦合到的存在预测器的性能来阻止未过滤的指示。 预测存在预测器还包括耦合到多个动态滤波器的失速确定逻辑。 停止确定逻辑被配置为基于从多个动态过滤器接收的一个或多个非阻塞指示来生成将停止指令传递的允许潜在潜在指令预测的组合指示。

    Instruction filtering
    4.
    发明授权
    Instruction filtering 有权
    指令过滤

    公开(公告)号：US09135012B2

    公开(公告)日：2015-09-15

    申请号：US13523170

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

    摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

    摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

    Cache memory prefetching
    5.
    发明授权
    Cache memory prefetching 有权

    公开(公告)号：US08966185B2

    公开(公告)日：2015-02-24

    申请号：US13523589

    申请日：2012-06-14

    申请人： Brian R. Prasky ,  Chung-Lung K. Shum

    发明人： Brian R. Prasky ,  Chung-Lung K. Shum

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/6024 ,  Y02D10/13

    摘要： According to exemplary embodiments, a computer program product, system, and method for prefetching in memory include determining a missed access request for a first line in a first cache level and accessing an entry in a prefetch table, wherein the entry corresponds to a memory block, wherein the entry includes segments of the memory block. Further, the embodiment includes determining a demand segment of the segments in the entry, the demand segment corresponding to a segment of the memory block that includes the first line, reading a first field in the demand segment to determine if a second line in the demand segment is spatially related with respect to accesses of the demand segment and reading a second field in the demand segment to determine if a second segment in the entry is temporally related to the demand segment.

    Process identifier-based cache data transfer
    7.
    发明授权
    Process identifier-based cache data transfer 有权
    基于进程标识符的缓存数据传输

    公开(公告)号：US08904100B2

    公开(公告)日：2014-12-02

    申请号：US13493636

    申请日：2012-06-11

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    IPC分类号： G06F12/02

    CPC分类号： G06F17/30982 ,  G06F12/0817 ,  G06F12/12

    摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.

    摘要翻译： 本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。 本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。 本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。 本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。 本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

    MITIGATING INSTRUCTION PREDICTION LATENCY WITH INDEPENDENTLY FILTERED PRESENCE PREDICTORS
    8.
    发明申请
    MITIGATING INSTRUCTION PREDICTION LATENCY WITH INDEPENDENTLY FILTERED PRESENCE PREDICTORS 有权
    与独立过滤的预测者进行预防指示预测失效

    公开(公告)号：US20130339692A1

    公开(公告)日：2013-12-19

    申请号：US13523784

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/38 ,  G06F9/3806 ,  G06F9/3848

    摘要： Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.

    摘要翻译： 本公开的实施例包括使用耦合到处理器管线的独立滤波的指令预测存在预测器来减轻指令预测等待时间。 预测存在预测器包括多个存在预测器，其被配置为并行地接收指令地址并且生成相关联的指令预测的未过滤的指示。 预测存在预测器包括多个动态滤波器，每个动态滤波器耦合到多个存在预测器之一。 每个动态过滤器被配置为基于其耦合到的存在预测器的性能来阻止未过滤的指示。 预测存在预测器还包括耦合到多个动态滤波器的失速确定逻辑。 停止确定逻辑被配置为基于从多个动态过滤器接收的一个或多个非阻塞指示来生成将停止指令传递的允许潜在潜在指令预测的组合指示。

    COLLISION-BASED ALTERNATE HASHING
    9.
    发明申请
    COLLISION-BASED ALTERNATE HASHING 有权
    基于冲突的替代洗涤

    公开(公告)号：US20130339665A1

    公开(公告)日：2013-12-19

    申请号：US13524139

    申请日：2012-06-15

    申请人： Khary J. Alexander ,  Ilia Averbouch ,  Ariel J. Birnbaum ,  Jonathan T. Hsieh ,  Chung-Lung K. Shum

    发明人： Khary J. Alexander ,  Ilia Averbouch ,  Ariel J. Birnbaum ,  Jonathan T. Hsieh ,  Chung-Lung K. Shum

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3808 ,  G06F9/3814

    摘要： Embodiments relate to collision-based alternate hashing. An aspect includes receiving an incoming instruction address. Another aspect includes determining whether an entry for the incoming instruction address exists in a history table based on a hash of the incoming instruction address. Another aspect includes based on determining that the entry for the incoming instruction address exists in the history table, determining whether the incoming instruction address matches an address tag in the determined entry. Another aspect includes based on determining that the incoming instruction address does not match the address tag in the determined entry, determining whether a collision exists for the incoming instruction address. Another aspect includes based on determining that the collision exists for the incoming instruction address, activating alternate hashing for the incoming instruction address using an alternate hash buffer.

    摘要翻译： 实施例涉及基于冲突的交替散列。 一方面包括接收输入指令地址。 另一方面包括基于输入指令地址的散列来确定历史表中是否存在输入指令地址的条目。 另一方面包括基于确定输入指令地址的条目存在于历史表中，确定输入指令地址是否匹配所确定条目中的地址标签。 另一方面包括基于确定输入指令地址与所确定的条目中的地址标签不匹配，确定对于输入指令地址是否存在冲突。 另一方面包括基于确定对于输入指令地址存在冲突，使用替代散列缓冲器激活输入指令地址的替换散列。