公开(公告)号：US09891922B2

公开(公告)日：2018-02-13

申请号：US13524402

申请日：2012-06-15

申请人： James J. Bonanno ,  Ulrich Mayer ,  Anthony Saporito ,  Chung-Lung K. Shum ,  Timothy J. Slegel

发明人： James J. Bonanno ,  Ulrich Mayer ,  Anthony Saporito ,  Chung-Lung K. Shum ,  Timothy J. Slegel

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/38 ,  G06F9/30076 ,  G06F9/3844 ,  G06F9/3848

摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.

公开(公告)号：US09235419B2

公开(公告)日：2016-01-12

申请号：US13492997

申请日：2012-06-11

申请人： James J. Bonanno ,  Ulrich Mayer ,  Brian R. Prasky

发明人： James J. Bonanno ,  Ulrich Mayer ,  Brian R. Prasky

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3806

摘要： Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry.

公开(公告)号：US08909879B2

公开(公告)日：2014-12-09

申请号：US13493644

申请日：2012-06-11

申请人： James J. Bonanno ,  Brian R. Prasky

发明人： James J. Bonanno ,  Brian R. Prasky

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F11/07 ,  G06F12/12

CPC分类号： G06F12/0891 ,  G06F11/076 ,  G06F12/00 ,  G06F12/0802 ,  G06F12/12 ,  G06F13/385

摘要： Embodiments of the invention relate to counter-based entry invalidation for a metadata previous write queue (PWQ). An aspect of the invention includes writing an address into an entry in the metadata PWQ, the address being associated with an instance of metadata received from a pipeline and setting a valid tag associated with the entry in the metadata PWQ to valid. Another aspect of the invention includes initializing a counter to zero and incrementing the counter based on receiving a count signal from the pipeline until the counter is equal to a threshold. Yet another aspect of the invention includes setting the valid tag to invalid based on the counter being equal to the threshold.

摘要翻译： 本发明的实施例涉及元数据先前写入队列（PWQ）的基于反向条目的无效。 本发明的一个方面包括将地址写入元数据PWQ中的条目中，该地址与从流水线接收的元数据实例相关联，并且将与元数据PWQ中的条目相关联的有效标签设置为有效。 本发明的另一方面包括：将计数器初始化为零，并基于从流水线接收计数信号递增计数器，直到计数器等于阈值。 本发明的另一方面包括基于等于阈值的计数器将有效标签设置为无效。

公开(公告)号：US20130339691A1

公开(公告)日：2013-12-19

申请号：US13517779

申请日：2012-06-14

申请人： James J. Bonanno ,  Marcel Mitran ,  Brian R. Prasky ,  Joran Siu ,  Timothy J. Slegel ,  Alexander Vasilevskiy

发明人： James J. Bonanno ,  Marcel Mitran ,  Brian R. Prasky ,  Joran Siu ,  Timothy J. Slegel ,  Alexander Vasilevskiy

IPC分类号： G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3806 ,  G06F9/3844

摘要： Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address.

摘要翻译： 实施例涉及分支预测预加载。 一方面包括用于分支预测预加载的系统。 该系统包括耦合到处理电路的指令高速缓存和分支目标缓冲器（BTB），所述处理电路被配置为执行方法。 该方法包括从指令高速缓冲存储器中取出指令流中的多个指令，以及对指令流中的分支预测预加载指令进行解码。 基于分支预测预加载指令来确定预测转移指令的地址。 基于分支预测预加载指令来确定预测目标地址。 在分支预测预加载指令中识别掩码字段，并且基于掩码字段来确定分支指令长度。 基于执行分支预测预加载指令，BTB预先加载预测分支指令的地址，分支指令长度，分支类型和预测目标地址。

公开(公告)号：US20130339683A1

公开(公告)日：2013-12-19

申请号：US13523170

申请日：2012-06-14

申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

公开(公告)号：US20090204799A1

公开(公告)日：2009-08-13

申请号：US12029547

申请日：2008-02-12

申请人： James J. Bonanno ,  Brian R. Prasky

发明人： James J. Bonanno ,  Brian R. Prasky

IPC分类号： G06F9/32

CPC分类号： G06F9/3806 ,  G06F9/3844

摘要： System and method for reducing branch prediction latency using a branch target buffer with most recently used column prediction. An exemplary embodiment includes a method for reducing branch prediction latency, the method including reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry corresponds to one or more branch target buffer rows and specifies the ordering from least-recently-used to most-recently-used of the associated branch target buffer columns, selecting a row from the branch target buffer and simultaneously selecting the associated entry from the most-recently-used table and speculating that there is a prediction in the most recently used column of the plurality of columns from the selected row from the branch target buffer while determining whether there is a prediction and which column contains the prediction.

摘要翻译： 使用最近使用的列预测的分支目标缓冲器来减少分支预测等待时间的系统和方法。 示例性实施例包括用于减少分支预测等待时间的方法，所述方法包括从与分支目标缓冲器相关联的最近使用的表中读取最近使用的信息，其中每个最近使用的条目对应于一个或多个分支 目标缓冲区行，并指定从最近最近使用到最近使用的关联分支目标缓冲区列的排序，从分支目标缓冲区中选择一行，同时从最近使用的表中选择相关联的条目， 推测在来自分支目标缓冲器的所选行的多列中的最近使用的列中存在预测，同时确定是否存在预测，哪个列包含预测。

公开(公告)号：US20130332683A1

公开(公告)日：2013-12-12

申请号：US13493644

申请日：2012-06-11

申请人： James J. Bonanno ,  Brian R. Prasky

发明人： James J. Bonanno ,  Brian R. Prasky

IPC分类号： G06F12/00

CPC分类号： G06F12/0891 ,  G06F11/076 ,  G06F12/00 ,  G06F12/0802 ,  G06F12/12 ,  G06F13/385

摘要： Embodiments of the invention relate to counter-based entry invalidation for a metadata previous write queue (PWQ). An aspect of the invention includes writing an address into an entry in the metadata PWQ, the address being associated with an instance of metadata received from a pipeline and setting a valid tag associated with the entry in the metadata PWQ to valid. Another aspect of the invention includes initializing a counter to zero and incrementing the counter based on receiving a count signal from the pipeline until the counter is equal to a threshold. Yet another aspect of the invention includes setting the valid tag to invalid based on the counter being equal to the threshold.

摘要翻译： 本发明的实施例涉及元数据先前写入队列（PWQ）的基于反向条目的无效。 本发明的一个方面包括将地址写入元数据PWQ中的条目中，该地址与从流水线接收的元数据实例相关联，并且将与元数据PWQ中的条目相关联的有效标签设置为有效。 本发明的另一方面包括：将计数器初始化为零，并基于从流水线接收计数信号递增计数器，直到计数器等于阈值。 本发明的另一方面包括基于等于阈值的计数器将有效标签设置为无效。

公开(公告)号：US07913068B2

公开(公告)日：2011-03-22

申请号：US12035109

申请日：2008-02-21

申请人： James J. Bonanno ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Anthony Saporito ,  Chung-Lung Kevin Shum

发明人： James J. Bonanno ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Anthony Saporito ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/42

CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/30174 ,  G06F9/3806

摘要： A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit.

摘要翻译： 提供了一种用于在处理器中进行异步动态毫代码入口预测的系统和方法。 该系统包括用于保存分支信息的分支目标缓冲器（BTB）。 分支信息包括：分支类型，指示分支表示针对毫微米子例程的毫米条目（中心）指令，以及与中心指令相关联的指令长度代码（ILC）。 该系统还包括执行方法的搜索逻辑。 该方法包括将BTB中的分支地址定位为针对毫秒子程序的中心指令，以及根据中心指令和ILC的指令地址确定返回地址以从millicode子程序返回。 该系统还包括指令获取控制以获取与搜索逻辑异步的毫微数子程序的指令。 搜索逻辑也可以相对于指令解码单元进行异步操作。

公开(公告)号：US07895538B2

公开(公告)日：2011-02-22

申请号：US12033974

申请日：2008-02-20

申请人： David S. Hutton ,  James J. Bonanno ,  Michael P. Mullen ,  Chung-Lung Kevin Shum

发明人： David S. Hutton ,  James J. Bonanno ,  Michael P. Mullen ,  Chung-Lung Kevin Shum

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/68

摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.

摘要翻译： 系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。 该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。 该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。 对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。

公开(公告)号：US07822954B2

公开(公告)日：2010-10-26

申请号：US12034112

申请日：2008-02-20

申请人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

发明人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/383 ,  G06F9/3802 ,  G06F9/3861

摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.

摘要翻译： 分支预测算法用于生成是否采用分支的预测。 取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。 执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。 当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。