公开(公告)号：US20080093748A1

公开(公告)日：2008-04-24

申请号：US11544934

申请日：2006-10-10

Applicant: Cheng-Pin Chen

Inventor： Cheng-Pin Chen

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/52 ,  H01L23/28

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/3142 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

公开(公告)号：USD304504S

公开(公告)日：1989-11-07

申请号：US867747

申请日：1986-05-28

Applicant: Cheng Pin Chen

Designer： Cheng Pin Chen

公开(公告)号：US20110100442A1

公开(公告)日：2011-05-05

申请号：US12870248

申请日：2010-08-27

Applicant: Jian-Jang Huang ,  Cheng-Pin Chen ,  Pei-Hsuan Lin

Inventor： Jian-Jang Huang ,  Cheng-Pin Chen ,  Pei-Hsuan Lin

IPC: H01L31/04

CPC classification number: H01L31/065 ,  B82Y20/00 ,  H01L31/0296 ,  H01L31/032 ,  H01L31/0324 ,  H01L31/035236 ,  Y02E10/50

Abstract: A structure of a solar cell. The structure of the solar cell includes a substrate, a graded layer and a semiconductor layer. The graded layer is disposed on the substrate. The graded layer is made from materials including the first material and the second material, and includes at least one thin film. One of the at least one thin film includes a mixture of at least the first material and the second material at a mixture ratio. The mixture forms a bandgap of the at least one thin film. The semiconductor layer is disposed on the graded layer.

Abstract translation: 太阳能电池的结构。 太阳能电池的结构包括基板，梯度层和半导体层。 分级层设置在基板上。 分级层由包括第一材料和第二材料的材料制成，并且包括至少一个薄膜。 所述至少一个薄膜中的一个以混合比包括至少第一材料和第二材料的混合物。 混合物形成至少一个薄膜的带隙。 半导体层设置在分级层上。

公开(公告)号：US20090127679A1

公开(公告)日：2009-05-21

申请号：US11984772

申请日：2007-11-21

Applicant: Wen-Jeng Fan ,  Cheng-Pin Chen

Inventor： Wen-Jeng Fan ,  Cheng-Pin Chen

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen.

Abstract translation: 具有在外部引线之间的焊接接头的封装保护的POP（封装封装）半导体器件主要包括多个堆叠的半导体封装和电介质涂层。 每个半导体封装包括至少一个芯片，多个引线框的外部引线以及外部引线从密封剂的多个侧面露出和延伸的密封剂。 顶部半导体封装的多个外部引线的端子焊接到底部半导体封装的相应外部引线的焊接区域。 电介质涂层沿着底部半导体封装的密封剂的侧面设置，以将焊接点连接到外部引线之间并且部分或完全地封装焊接材料，使得焊接接头之间的应力可以分散并且不发生电短路 。

公开(公告)号：US20080099890A1

公开(公告)日：2008-05-01

申请号：US11589155

申请日：2006-10-30

Applicant: Cheng-Pin Chen ,  Wen-Jeng Fan ,  Li-chih Fang

Inventor： Cheng-Pin Chen ,  Wen-Jeng Fan ,  Li-chih Fang

IPC: H01L23/495

CPC classification number: H01L23/3128 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/0655 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18301 ,  H01L2924/00

Abstract: A ball grid array package structure includes: a substrate having at least one chip bearing area on its upper surface and a plurality of electrical-connecting points on its lower surface; a plurality of chips are arranged on the chip bearing area and electrically connected with those electrical-connecting points; a plurality of through holes penetrating the substrate at the edge of chip bearing area; an encapsulant used to cover those chip and filling those through holes to form a strengthened bump surrounding the chip bearing area on the lower surface of the substrate; and a plurality of conductive balls are respectively arranged on those electrical-connecting points. The present invention utilizes the strengthened bump on the bottom of the substrate to enhance the structure strength of the substrate so as to avoid the warpage of the substrate caused from the stress due to the temperature variation during the package process to affect the following processes.

Abstract translation: 球栅阵列封装结构包括：在其上表面上具有至少一个芯片支承区域的基板和其下表面上的多个电连接点; 多个芯片布置在芯片支承区域上并与那些电连接点电连接; 在芯片承载区域的边缘处穿过基板的多个通孔; 用于覆盖那些芯片并填充这些芯片的密封剂，以形成围绕衬底的下表面上的芯片支承区域的加强凸块; 并且在这些电连接点上分别布置有多个导电球。 本发明利用基板底部的加强凸块来增强基板的结构强度，以避免由于包装过程中的温度变化而引起的应力引起的基板翘曲影响以下工艺。

公开(公告)号：US20110048528A1

公开(公告)日：2011-03-03

申请号：US12788252

申请日：2010-05-26

Applicant: Jian-Jang HUANG ,  Cheng-Pin Chen ,  Pei-Hsuan Lin

Inventor： Jian-Jang HUANG ,  Cheng-Pin Chen ,  Pei-Hsuan Lin

IPC: H01L31/00

CPC classification number: H01L31/0236 ,  H01L31/0547 ,  Y02E10/52

Abstract: A structure of a solar cell is provided. The structure of the solar cell includes a substrate, a base and a plurality of nanostructures. The base is disposed on the substrate. The nanostructures are disposed on a surface of the base, or a surface of the base includes the nanostructures, so as to increase light absorption of the structure.

Abstract translation: 提供太阳能电池的结构。 太阳能电池的结构包括基底，基底和多个纳米结构。 底座设置在基板上。 纳米结构设置在基底的表面上，或者基底的表面包括纳米结构，以增加结构的光吸收。

公开(公告)号：US07692311B2

公开(公告)日：2010-04-06

申请号：US11984772

申请日：2007-11-21

Applicant: Wen-Jeng Fan ,  Cheng-Pin Chen

Inventor： Wen-Jeng Fan ,  Cheng-Pin Chen

IPC: H01L23/12

CPC classification number: H01L23/4951 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen.

Abstract translation: 具有在外部引线之间的焊接接头的封装保护的POP（封装封装）半导体器件主要包括多个堆叠的半导体封装和电介质涂层。 每个半导体封装包括至少一个芯片，多个引线框的外部引线以及外部引线从密封剂的多个侧面露出和延伸的密封剂。 顶部半导体封装的多个外部引线的端子焊接到底部半导体封装的相应外部引线的焊接区域。 电介质涂层沿着底部半导体封装的密封剂的侧面设置，以将焊接点连接到外部引线之间并且部分或完全地封装焊接材料，使得焊接接头之间的应力可以分散并且不发生电短路 。

公开(公告)号：US07432601B2

公开(公告)日：2008-10-07

申请号：US11544934

申请日：2006-10-10

Applicant: Cheng-Pin Chen

Inventor： Cheng-Pin Chen

IPC: H01L21/00

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/3142 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

Abstract translation: 半导体封装主要包括芯片，衬底，密封剂，多个外部端子和应力释放层。 基板具有上表面和下表面。 芯片通过芯片附着层设置在基板的上表面上并与基板电连接。 密封剂形成在衬底的上表面上方。 外部端子设置在基板的下表面上。 应力释放层形成在基板和密封剂的界面上，使得外部端子相对于封装的芯片是可移动的。 此外，还公开了半导体封装的制造工艺。

公开(公告)号：US20070257345A1

公开(公告)日：2007-11-08

申请号：US11508829

申请日：2006-08-24

Applicant: Wen-Jeng Fan ,  Cheng-Pin Chen ,  Li-chih Fang

Inventor： Wen-Jeng Fan ,  Cheng-Pin Chen ,  Li-chih Fang

IPC: H01L23/02

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/97 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A package structure includes: a substrate having a chip-bearing area arranged thereon; an window type assistant element arranged on the substrate and surrounding the edge of the chip-bearing area; a plurality of chips arranged within the chip-bearing area; and a package encapsulation covering chips within the chip-bearing area. It can resist the deformation and reduce the damage from the warpage and simultaneously enhance the yield and stability of the package structure.

Abstract translation: 包装结构包括：其上布置有芯片承载区域的基板; 窗口型辅助元件，布置在基板上并围绕芯片承载区域的边缘; 布置在所述芯片承载区域内的多个芯片; 以及在芯片承载区域内覆盖芯片的封装封装。 可以抵抗变形，减少翘曲的损伤，同时提高包装结构的产量和稳定性。