公开(公告)号：US6015749A

公开(公告)日：2000-01-18

申请号：US72004

申请日：1998-05-04

Applicant: Chung-Shi Liu ,  Chen-Hua Douglas Yu ,  Jane-Bai Lai ,  Lih-Juann Chen

Inventor： Chung-Shi Liu ,  Chen-Hua Douglas Yu ,  Jane-Bai Lai ,  Lih-Juann Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002

Abstract: A method for fabricating a copper interconnect structure, using a Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following the deposition of a copper seed layer, an ion implantation procedure is performed, placing germanium ions in a copper seed layer. After deposition of a thick copper layer, an anneal cycle, performed before or after deposition of the thick copper layer, is used to create a Cu.sub.3 Ge intermetallic layer at the interface between a copper seed layer and a titanium nitride barrier layer. A second embodiment of this invention uses a tilted, germanium ion implantation procedure, used to avoid the placement of germanium ions in a copper seed layer, at the bottom of a contact hole, thus avoiding possible implantation damage, to active device regions, exposed in the bottom of the contact hole.

Abstract translation: 已经开发了使用Cu 3 Ge金属间化合物作为粘合剂层的铜互连结构的制造方法。 在沉积铜籽晶层之后，进行离子注入程序，将锗离子放置在铜籽晶层中。 在沉积厚铜层之后，在沉积厚铜层之前或之后执行的退火循环用于在铜籽晶层和氮化钛阻挡层之间的界面处产生Cu 3 Ge金属间化合物层。 本发明的第二实施例使用倾斜的锗离子注入程序，用于避免将锗离子放置在铜种子层中，在接触孔的底部，从而避免可能的植入损伤，暴露于有源器件区域 接触孔的底部。

公开(公告)号：US5679606A

公开(公告)日：1997-10-21

申请号：US579518

申请日：1995-12-27

Applicant: Chin-Kun Wang ,  Chen-Hua Douglas Yu ,  Lu-Min Lin

Inventor： Chin-Kun Wang ,  Chen-Hua Douglas Yu ,  Lu-Min Lin

IPC: H01L21/768 ,  H01L21/316

CPC classification number: H01L21/76837 ,  H01L21/76832 ,  H01L21/76834

Abstract: A process for forming an planar dielectric layer over metallurgy lines using an in situ multi-step electron cyclotron resonance (ECR) oxide deposition process. A substrate with metallurgy lines on its surface is covered with a protective ECR oxide layer. The novel ECR process for the protective layer does not have an argon flow and does not etch the surface (e.g., metal lines) it is deposited upon. Next, a gap-fill step is formed over the protective layer. The gap-fill step uses Argon flow and rf power to enhance the deposition in gaps and the planarization. The gap-fill layer etches the underlying protective layer but the protective layer prevents the gap-fill deposition/etch process from attacking and damaging the metallurgy lines. Next, the protective layer and the gap-fill layer sequence are repeated until the desired thickness is obtained. A thick capping protective layer and a capping gap-fill layer are used to complete the planarization process. This multi-step in situ process permits the use of the corrosive Gap-fill ECR process which can fill between closely spaced metallurgy lines without damaging the lines.

Abstract translation: 使用原位多步骤电子回旋共振（ECR）氧化物沉积工艺在冶金线上形成平面介电层的方法。 在其表面上具有冶金线的衬底被保护性ECR氧化物层覆盖。 用于保护层的新型ECR工艺不具有氩气流并且不蚀刻其沉积的表面（例如，金属线）。 接下来，在保护层上形成间隙填充步骤。 间隙填充步骤使用氩气流和射频功率来增强间隙中的沉积和平坦化。 间隙填充层蚀刻下面的保护层，但保护层防止间隙填充沉积/蚀刻工艺攻击和损坏冶金生产线。 接下来，重复保护层和间隙填充层序列，直到获得所需的厚度。 使用厚封盖保护层和封盖间隙填充层来完成平坦化工艺。 这种多步原位工艺允许使用可以填充在紧密间隔的冶金生产线之间的腐蚀性间隙填充ECR工艺，而不会损坏管线。

公开(公告)号：US6083829A

公开(公告)日：2000-07-04

申请号：US083419

申请日：1998-05-22

Applicant: Jane-Bai Lai ,  Lih-Juann Chen ,  Chung-Shi Liu ,  Chen-Hua Douglas Yu

Inventor： Jane-Bai Lai ,  Lih-Juann Chen ,  Chung-Shi Liu ,  Chen-Hua Douglas Yu

IPC: C23C16/56 ,  C23C26/00 ,  C23C28/00 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76873 ,  C23C16/56 ,  C23C26/00 ,  C23C28/00 ,  H01L21/2885 ,  H01L21/321 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/53238 ,  H01L2924/0002

Abstract: A method for fabricating a copper interconnect structure, using a low resistivity Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copper layer, an anneal procedure is used to form the Cu.sub.3 Ge intermetallic layer, with the intermetallic layer, located between the underlying titanium nitride barrier layer, and the overlying copper layer. The Cu.sub.3 Ge intermetallic layer can also be formed in situ, during deposition, if the deposition temperature exceeds 150.degree. C. Cu.sub.3 Ge layer exhibits a resistivity of about 5E-6 ohm - cm. A second iteration of this invention allows a thick copper layer to be plated on a thin copper seed layer, only on the top surface of a semiconductor substrate. This iteration, also incorporating the low resistivity, Cu.sub.3 Ge intermetallic, and the adhesive layer, prevents copper from being plated on the beveled edge of the semiconductor substrate.

Abstract translation: 已经开发了使用低电阻率Cu 3 Ge金属间化合物作为粘合剂层的铜互连结构的制造方法。 在原位，氮化钛阻挡层，锗层和铜层的CVD之后，使用退火程序形成Cu 3 Ge金属间化合物层，金属间层位于下面的氮化钛阻挡层和 上覆铜层。 如果沉积温度超过150℃，Cu3Ge金属间化合物层也可以在沉积过程中原位形成。Cu3Ge层的电阻率约为5E-6欧姆 - 厘米。 本发明的第二次迭代允许厚铜层仅在半导体衬底的顶表面上镀覆在薄铜籽晶层上。 也包含低电阻率Cu3Ge金属间化合物和粘合剂层的这种迭代防止铜电镀在半导体衬底的斜边上。

公开(公告)号：US5904563A

公开(公告)日：1999-05-18

申请号：US650699

申请日：1996-05-20

Applicant: Chen-Hua Douglas Yu

Inventor： Chen-Hua Douglas Yu

IPC: H01L23/544 ,  H01L21/64

CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

Abstract: The contact hole via mask used in the manufacture of semiconductor integrated circuits is modified to produce a multiplicity of lines and spaces adjacent to the edge of an alignment mark in the via hole pattern. This line-space pattern is etched simultaneously with the contact via holes, and allows the regeneration of the alignment mark after tungsten deposition and planarization of the surface by conventional oxide etching and metallization steps.

Abstract translation: 在半导体集成电路的制造中使用的接触孔通孔掩模被修改以产生与通孔图案中的对准标记的边缘相邻的多个线和间隔。 该线间隔图案与接触通孔同时蚀刻，并且通过常规的氧化物蚀刻和金属化步骤，在钨沉积和表面平坦化之后允许对准标记的再生。

公开(公告)号：US5904559A

公开(公告)日：1999-05-18

申请号：US967916

申请日：1997-11-12

Applicant: Chen-Hua Douglas Yu

Inventor： Chen-Hua Douglas Yu

IPC: H01L21/768 ,  H01L21/31

CPC classification number: H01L21/76807 ,  H01L21/76838

Abstract: A process has been developed in which the contact area, between an overlying metal filled via structure, and an underlying metal interconnect structure, has been increased. The process features opening a via hole, in a dielectric layer, to an underlying metal interconnect structure, with the via hole being larger in width then the width of the underlying metal interconnect structure. Continued selective removal of the dielectric layer, in the via hole, results in exposure of the sides of the metal interconnect structure. Subsequent formation of an overlying metal filled via structure, in the via hole, results in an increase in contact area between the overlying metal filled via structure, and the narrow, metal interconnect structure.

Abstract translation: 已经开发了一种方法，其中覆盖金属填充的通孔结构和下面的金属互连结构之间的接触面积已经增加。 该工艺特征是在介电层中打开通孔到下面的金属互连结构，其中通孔宽度越大，下面的金属互连结构的宽度越宽。 在通孔中继续选择性地去除电介质层导致金属互连结构的侧面的曝光。 随后在通孔中形成上覆金属填充的通孔结构导致上覆金属填充的通孔结构与窄金属互连结构之间的接触面积增加。

公开(公告)号：US5880022A

公开(公告)日：1999-03-09

申请号：US815316

申请日：1991-12-30

Applicant: Kuo-Hua Lee ,  Chen-Hua Douglas Yu

Inventor： Kuo-Hua Lee ,  Chen-Hua Douglas Yu

IPC: H01L21/336 ,  H01L21/60 ,  H01L29/78 ,  H01L21/441 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L29/66575

Abstract: A self aligned contact to the substrate in the region between two gate electrodes is formed by depositing a conformal dielectric layer and patterning to form a contact window. The conductive elements of the gate electrode are not contacted because of etch rate differentials between the conformal dielectric and the insulating elements of the gate structure.

Abstract translation: 在两个栅电极之间的区域中与衬底的自对准接触通过沉积保形电介质层并图案化以形成接触窗而形成。 由于保形电介质和栅极结构的绝缘元件之间的蚀刻速率差异，栅电极的导电元件不接触。

公开(公告)号：US5817571A

公开(公告)日：1998-10-06

申请号：US661286

申请日：1996-06-10

Applicant: Chen-Hua Douglas Yu ,  Syun-Ming Jang ,  Huang Yuan-Chang

Inventor： Chen-Hua Douglas Yu ,  Syun-Ming Jang ,  Huang Yuan-Chang

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31055 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76819

Abstract: A method for forming a planarized interlevel dielectric layer without degradation due to microloading effect is described. A first conformal layer of silicon dioxide is deposited overlying a conducting layer over an insulating layer on a semiconductor substrate. A second silicon dioxide layer is deposited overlying the first conformal silicon dioxide layer. A doped glass layer is deposited overlying the second silicon dioxide layer. The doped glass layer is coated with a spin-on-glass layer. The spin-on-glass layer is etched back until the interlevel dielectric layer is planarized. The microloading effects from the etching back of the spin-on-glass layer of the interlevel dielectric layer are lower than microloading effects in a conventional interlevel dielectric layer.

Abstract translation: 描述了由于微加载效应而形成平坦化层间电介质层而不降解的方法。 沉积在半导体衬底上的绝缘层上的导电层的第一保形二氧化硅层。 沉积第二二氧化硅层，覆盖第一共形二氧化硅层。 沉积覆盖第二二氧化硅层的掺杂玻璃层。 掺杂的玻璃层涂覆有旋涂玻璃层。 将旋涂玻璃层回蚀刻直到层间介质层平坦化。 层间电介质层的旋转玻璃层的蚀刻后的微载荷效应低于常规层间电介质层中的微载荷效应。

公开(公告)号：US5728619A

公开(公告)日：1998-03-17

申请号：US618890

申请日：1996-03-20

Applicant: Chia Shiung Tsai ,  Chen-Hua Douglas Yu

Inventor： Chia Shiung Tsai ,  Chen-Hua Douglas Yu

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/336

CPC classification number: H01L21/31116 ,  H01L21/76816

Abstract: A method for forming within an integrated circuit a narrow line-width high aspect ratio via through a first integrated circuit layer which resides upon a second integrated circuit layer. There is first formed upon a semiconductor substrate a second integrated circuit layer which has formed upon its surface a first integrated circuit layer. Through a first etch method, a partial via is then formed within the first integrated circuit layer to a distance of from about 2500 to about 4000 angstroms above the surface of the second integrated circuit layer. The first etch method is chosen to provide a partial via with substantially parallel sidewalls. Through a second etch method, the partial via is then etched completely through the first integrated circuit layer. The second etch method is chosen to possesses an etch selectivity ratio for the first integrated circuit layer with respect to the second integrated circuit layer of at least about 60:1. The method is preferably employed in forming narrow line-width high aspect ratio vias through insulator layers beneath which reside metal silicide layers formed upon integrated circuit device electrodes within integrated circuits.

Abstract translation: 一种在集成电路内通过位于第二集成电路层上的第一集成电路层形成窄线宽高宽比通孔的方法。 首先在半导体衬底上形成第二集成电路层，该第二集成电路层在其表面上形成第一集成电路层。 通过第一蚀刻方法，然后在第一集成电路层内形成部分通孔至第二集成电路层表面之上约2500至约4000埃的距离。 选择第一蚀刻方法以提供具有基本上平行的侧壁的部分通孔。 通过第二蚀刻方法，然后通过第一集成电路层完全蚀刻部分通孔。 第二蚀刻方法被选择为具有相对于第二集成电路层的至少约60:1的第一集成电路层的蚀刻选择率。 该方法优选用于通过绝缘体层形成狭窄的线宽高纵横比通孔，在绝缘层下方在集成电路内的集成电路器件电极上形成金属硅化物层。

公开(公告)号：US6072237A

公开(公告)日：2000-06-06

申请号：US163382

申请日：1998-09-30

Applicant: Syun-Ming Jang ,  Chen-Hua Douglas Yu

Inventor： Syun-Ming Jang ,  Chen-Hua Douglas Yu

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01K23/04

CPC classification number: H01L23/53223 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

Abstract: A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.

Abstract translation: 已经开发了用于形成无边界，接触或通孔的方法，其中使用薄氮化硅层作为蚀刻停止件，以防止在无边界接触或通孔的打开期间侵入下面的层间电介质层 在叠层的层间电介质层中。 薄的氮化硅层是在金属互连层之间使用的层间介质复合层的顶层。

公开(公告)号：US6037018A

公开(公告)日：2000-03-14

申请号：US108866

申请日：1998-07-01

Applicant: Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

Inventor： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

IPC: C23C16/40 ,  H01L21/762 ,  B05D3/06 ,  H01L21/76

CPC classification number: H01L21/76232 ,  C23C16/402

Abstract: A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.

Abstract translation: 用HDPCVD氧化物50填充浅沟槽28的方法。本发明具有两个衬垫：（a）热氧化物衬垫36和（b）上覆的共形O3-TEOS保护衬垫40.O3-TEOS保护衬垫40防止 HDPCVD氧化物50从溅射破坏沟槽侧壁和掩模层24.O3-TEOS层具有新的工艺温度（400至560℃）和低压（40至80托），允许O 3 -TEOS层沉积 该方法开始于在衬底上形成衬垫氧化物层20和阻挡层24。 沟槽28通过衬垫氧化物层20和阻挡层24形成在衬底10中。热氧化物衬里36和保护性O 3 -TEOS衬里层40形成在沟槽28的壁上并且在阻挡层24上方 最后，在填充沟槽28的保护衬垫层40之上形成高密度等离子体化学气相沉积（HDPCVD）氧化物层50。