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公开(公告)号：US09001559B2
公开(公告)日：2015-04-07
申请号：US14018242
申请日：2013-09-04
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
摘要翻译： 根据一个实施例，电阻变化存储器包括存储单元，读出放大器和全局位线。 存储单元设置在局部位线和字线相交的位置。 存储单元连接到本地位线和字线。 读出放大器通过向存储单元提供读取电流来读取存储在存储单元上的数据。 全局位线连接在本地位线和读出放大器之间。 全局位线将由读出放大器提供的读取电流馈送到本地位线。 在本地位线和全局位线彼此连接之前，读出放大器对全局位线进行充电。
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公开(公告)号：US20140286081A1
公开(公告)日：2014-09-25
申请号：US14018242
申请日：2013-09-04
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
摘要翻译： 根据一个实施例，电阻变化存储器包括存储单元，读出放大器和全局位线。 存储单元设置在局部位线和字线相交的位置。 存储单元连接到本地位线和字线。 读出放大器通过向存储单元提供读取电流来读取存储在存储单元上的数据。 全局位线连接在本地位线和读出放大器之间。 全局位线将由读出放大器提供的读取电流馈送到本地位线。 在本地位线和全局位线彼此连接之前，读出放大器对全局位线进行充电。
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公开(公告)号：US09484091B2
公开(公告)日：2016-11-01
申请号：US14636740
申请日：2015-03-03
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
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公开(公告)号：US20140286075A1
公开(公告)日：2014-09-25
申请号：US14018287
申请日：2013-09-04
申请人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
发明人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
摘要翻译： 根据一个实施例，存储器包括存储单元阵列，其包括沿列方向布置的块，第一和第二主全局导线，每列从列方向上从存储单元阵列的第一端延伸到第二端，第一电阻 连接在存储单元阵列内部的第一和第二主要全局导电线之间的改变元件，从列方向上从存储单元阵列的第一端延伸到第二端的第一参考全局导电线，以及连接到存储单元阵列的第二电阻变化元件 到存储单元阵列外的参考全局导线。
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公开(公告)号：US09741434B2
公开(公告)日：2017-08-22
申请号：US14018287
申请日：2013-09-04
申请人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
发明人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
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公开(公告)号：US20150179252A1
公开(公告)日：2015-06-25
申请号：US14636740
申请日：2015-03-03
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
摘要翻译： 根据一个实施例，电阻变化存储器包括存储单元，读出放大器和全局位线。 存储单元设置在局部位线和字线相交的位置。 存储单元连接到本地位线和字线。 读出放大器通过向存储单元提供读取电流来读取存储在存储单元上的数据。 全局位线连接在本地位线和读出放大器之间。 全局位线将由读出放大器提供的读取电流馈送到本地位线。 在本地位线和全局位线彼此连接之前，读出放大器对全局位线进行充电。
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公开(公告)号：US20130308400A1
公开(公告)日：2013-11-21
申请号：US13592265
申请日：2012-08-22
申请人： Byoung Chan Oh , Yoon Jae Shin
发明人： Byoung Chan Oh , Yoon Jae Shin
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0038 , G11C13/0061 , G11C2013/0092
摘要： A write control device includes a switching unit configured to selectively supply a write current in response to a driving control signal, a driving unit configured to supply a driving current to a memory cell corresponding to the write current applied through the switching unit, and an over-driving control unit coupled to an output node of the driving unit and configured to over-drive the output node in response to the driving control signal.
摘要翻译： 写控制装置包括：开关单元，被配置为响应于驱动控制信号选择性地提供写入电流;驱动单元，被配置为向与通过开关单元施加的写入电流相对应的存储单元提供驱动电流， 驱动控制单元耦合到所述驱动单元的输出节点并且被配置为响应于所述驱动控制信号而过驱动所述输出节点。
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8.发明申请ELECTRONIC DEVICE INCLUDING SEMICONDUCTOR MEMORY AND OPERATION METHOD THEREOF 审中-公开包括半导体存储器的电子器件及其操作方法公开(公告)号：US20150302925A1
公开(公告)日：2015-10-22
申请号：US14560819
申请日：2014-12-04
申请人： Byoung-Chan OH , Ji-Hyae BAE , Katsuyuki FUJITA , Yutaka SHIRAI
发明人： Byoung-Chan OH , Ji-Hyae BAE , Katsuyuki FUJITA , Yutaka SHIRAI
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C2013/0076 , G11C2013/0078 , G11C2213/79 , G11C2213/82
摘要： Disclosed is an electronic device including a semiconductor memory. The semiconductor memory includes a bit line, a source line, a plurality of resistive memory cells among which a selected resistive memory cell forms a current path between the bit line and the source line, a sense amplifier suitable for sensing data of the bit line in an active operation, a latch suitable for latching data sensed by the sense amplifier in the active operation, a write control unit suitable for comparing data latched in the latch with write data in a write operation, and a write driver suitable for driving the bit line and the source line based on a comparison result of the write control unit and the write data in the write operation.
摘要翻译： 公开了一种包括半导体存储器的电子设备。 半导体存储器包括位线，源极线，多个电阻存储器单元，其中所选择的电阻性存储单元在位线和源极线之间形成电流路径，适于感测位线的数据的读出放大器 一个有效的操作，一个适合于在激活的操作中锁存由读出放大器感测的数据的锁存器;一个写入控制单元，适合于将在锁存中锁存的数据与写入操作中的写入数据进行比较;以及写入驱动器，适用于驱动位线 以及基于写入操作的写入控制单元和写入数据的比较结果的源极线。
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公开(公告)号：US08879339B2
公开(公告)日：2014-11-04
申请号：US13592265
申请日：2012-08-22
申请人： Byoung Chan Oh , Yoon Jae Shin
发明人： Byoung Chan Oh , Yoon Jae Shin
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0038 , G11C13/0061 , G11C2013/0092
摘要： A write control device includes a switching unit configured to selectively supply a write current in response to a driving control signal, a driving unit configured to supply a driving current to a memory cell corresponding to the write current applied through the switching unit, and an over-driving control unit coupled to an output node of the driving unit and configured to over-drive the output node in response to the driving control signal.
摘要翻译： 写控制装置包括：开关单元，被配置为响应于驱动控制信号选择性地提供写入电流;驱动单元，被配置为向与通过开关单元施加的写入电流相对应的存储单元提供驱动电流， 驱动控制单元耦合到所述驱动单元的输出节点并且被配置为响应于所述驱动控制信号而过驱动所述输出节点。
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