公开(公告)号：US09367255B2

公开(公告)日：2016-06-14

申请号：US14855760

申请日：2015-09-16

Applicant: Eun-Jin Yun ,  Bogeun Kim

Inventor： Eun-Jin Yun ,  Bogeun Kim

IPC: G11C11/00 ,  G11C11/34 ,  G06F3/06 ,  G11C16/10 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G11C11/005 ,  G11C11/16 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C16/10

Abstract: A storage device includes a variable resistance memory, a flash memory and a controller. The flash memory includes a plurality of memory cells connected to a plurality of word lines. The controller is configured to receive data from an external device and program the received data in the variable resistance memory or the flash memory according to a quantity of data to be programmed in the flash memory. Further, the controller is configured to read from the variable resistance memory and program the read data in the flash memory, when the quantity of data accumulated in the variable resistance memory corresponds to a super page of data.

Abstract translation: 存储装置包括可变电阻存储器，闪存和控制器。 闪存包括连接到多个字线的多个存储单元。 控制器被配置为从外部设备接收数据，并根据要在闪速存储器中编程的数据量将接收到的数据编程到可变电阻存储器或闪存中。 此外，当可变电阻存储器中累积的数据量对应于数据的超级页面时，控制器被配置为从可变电阻存储器读取并对闪速存储器中的读取数据进行编程。

公开(公告)号：US08773908B2

公开(公告)日：2014-07-08

申请号：US13477161

申请日：2012-05-22

Applicant: Youngsun Song ,  Bogeun Kim ,  Ohsuk Kwon ,  Kitae Park ,  Seung-Hwan Shin ,  Sangyong Yoon

Inventor： Youngsun Song ,  Bogeun Kim ,  Ohsuk Kwon ,  Kitae Park ,  Seung-Hwan Shin ,  Sangyong Yoon

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。

公开(公告)号：US20110188310A1

公开(公告)日：2011-08-04

申请号：US13014237

申请日：2011-01-26

Applicant: BoGeun Kim

Inventor： BoGeun Kim

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/04 ,  G11C16/06

Abstract: A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line. Related methods of operating memory devices are also provided.

Abstract translation: 存储器件包括串联连接在位线和公共源极线和多个字线之间的多个存储器单元，其中各个字线连接到多个存储器单元的各个栅极。 存储器件还包括公共源极线补偿电路，该公共源极线补偿电路被配置为响应于公共源极线上的公共源极线电压而产生位线上的补偿偏置电压或多个字线中的至少一个字线。 还提供了操作存储器件的相关方法。

公开(公告)号：US20160004469A1

公开(公告)日：2016-01-07

申请号：US14855760

申请日：2015-09-16

Applicant: EUN-JIN YUN ,  BOGEUN KIM

Inventor： EUN-JIN YUN ,  BOGEUN KIM

IPC: G06F3/06 ,  G11C11/56

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G11C11/005 ,  G11C11/16 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C16/10

Abstract: An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory.

公开(公告)号：US08422292B2

公开(公告)日：2013-04-16

申请号：US13100134

申请日：2011-05-03

Applicant: Yoon-Hee Choi ,  BoGeun Kim

Inventor： Yoon-Hee Choi ,  BoGeun Kim

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.

Abstract translation: 非易失性存储器件及其编程方法执行包括选择性验证步骤和顺序验证步骤的编程验证步骤。 在选择性验证步骤中，数据输入/输出（I / O）电路根据存储数据的临时编程状态选择性地对所选位线进行预充电。 在顺序验证步骤中，数据I / O电路根据先前的选择性验证步骤的结果或先前的顺序验证步骤选择性地预充电每一位线。 根据编程方法，由于在编程验证步骤中不需要编程验证步骤的存储单元未被预充电，所以ON单元电流不流过其中。 因此，可以减少在验证期间流过公共源极线的电流。

公开(公告)号：US20140313835A1

公开(公告)日：2014-10-23

申请号：US14242406

申请日：2014-04-01

Applicant: Yongkyu Lee ,  BoGeun KIM

Inventor： Yongkyu Lee ,  BoGeun KIM

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/3418

Abstract: A data programming method of a semiconductor memory device is provided which includes randomizing write data using a randomization method selected from among a plurality of randomization methods according to whether the write data is programmed in one of a plurality of nonvolatile memories; and programming the randomized write data in at least one of the plurality of nonvolatile memories, wherein the plurality of nonvolatile memories has different types from one another.

Abstract translation: 提供一种半导体存储器件的数据编程方法，其包括使用根据所述写入数据是否被编程在多个非易失性存储器之一中的从多种随机化方法中选择的随机化方法来随机化写入数据; 以及将所述随机写入数据编程在所述多个非易失性存储器中的至少一个中，其中所述多个非易失性存储器具有彼此不同的类型。

公开(公告)号：US08446769B2

公开(公告)日：2013-05-21

申请号：US13014237

申请日：2011-01-26

Applicant: BoGeun Kim

Inventor： BoGeun Kim

IPC: G11C11/34

CPC classification number: G11C16/04 ,  G11C16/06

Abstract: A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line. Related methods of operating memory devices are also provided.

Abstract translation: 存储器件包括串联连接在位线和公共源极线和多个字线之间的多个存储器单元，其中各个字线连接到多个存储器单元的各个栅极。 存储器件还包括公共源极线补偿电路，该公共源极线补偿电路被配置为响应于公共源极线上的公共源极线电压而产生位线上的补偿偏置电压或多个字线中的至少一个字线。 还提供了操作存储器件的相关方法。

公开(公告)号：US20110280083A1

公开(公告)日：2011-11-17

申请号：US13100134

申请日：2011-05-03

Applicant: Yoon-Hee Choi ,  BoGeun Kim

Inventor： Yoon-Hee Choi ,  BoGeun Kim

IPC: G11C16/10 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.

Abstract translation: 非易失性存储器件及其编程方法执行包括选择性验证步骤和顺序验证步骤的编程验证步骤。 在选择性验证步骤中，数据输入/输出（I / O）电路根据存储数据的临时编程状态选择性地对所选位线进行预充电。 在顺序验证步骤中，数据I / O电路根据先前的选择性验证步骤的结果或先前的顺序验证步骤选择性地预充电每一位线。 根据编程方法，由于在编程验证步骤中不需要编程验证步骤的存储单元未被预充电，所以ON单元电流不流过其中。 因此，可以减少在验证期间流过公共源极线的电流。

公开(公告)号：US09864682B2

公开(公告)日：2018-01-09

申请号：US14664125

申请日：2015-03-20

Applicant: Doohyun Kim ,  BoGeun Kim ,  Kitae Park ,  Jinman Han

Inventor： Doohyun Kim ,  BoGeun Kim ,  Kitae Park ,  Jinman Han

IPC: G06F12/02 ,  G11C11/56 ,  G11C16/04

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G11C11/5621 ,  G11C16/0483

Abstract: According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.

公开(公告)号：US09165657B2

公开(公告)日：2015-10-20

申请号：US13803715

申请日：2013-03-14

Applicant: Eun-Jin Yun ,  Bogeun Kim

Inventor： Eun-Jin Yun ,  Bogeun Kim

IPC: G11C16/10 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G11C11/005 ,  G11C11/16 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C16/10

Abstract: An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory.

Abstract translation: 操作方法是用于存储器系统，其包括NAND闪存，电阻变量存储器以及控制NAND闪存和电阻变量存储器的控制器。 操作方法包括接收数据，在接收到的数据至少是数据的超级页面时对接收到的数据进行编程，当接收到的数据不是数据的超级页面时，对电阻变量存储器中的接收数据进行编程， 以及当累积的数据是数据的超级页面时，在NAND闪存中的电阻变量存储器中累积的编程数据。 数据的超级页面是可连接到NAND闪存的相同字线的存储器单元中的可编程数据的整体。