公开(公告)号：US20130106630A1

公开(公告)日：2013-05-02

申请号：US13287978

申请日：2011-11-02

申请人： Ark-Chew Wong ,  Olivier Jacques Nys

发明人： Ark-Chew Wong ,  Olivier Jacques Nys

IPC分类号： H03M1/38

CPC分类号： H03M1/46 ,  H03M1/747

摘要： Examples of systems and methods are provided for converting an analog input signal to a digital output signal. A system may include a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current. A comparator circuit may be configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal. A successive approximation register circuit may be configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal. The DAC-code signal may be used by the CM DAC circuit to control the DAC current.

摘要翻译： 提供了用于将模拟输入信号转换为数字输出信号的系统和方法的示例。 系统可以包括提供DAC电流的电流模式（CM）数模转换器（DAC）电路。 比较器电路可以被配置为响应于基于DAC电流和模拟输入信号确定的误差信号而产生比较器信号。 逐次逼近寄存器电路可以被配置为响应于比较器信号而产生DAC代码信号或数字输出信号中的至少一个。 DAC代码信号可被CM DAC电路用于控制DAC电流。

公开(公告)号：US20130106629A1

公开(公告)日：2013-05-02

申请号：US13282304

申请日：2011-10-26

申请人： Olivier NYS ,  Ark-Chew Wong

发明人： Olivier NYS ,  Ark-Chew Wong

IPC分类号： H03M1/38

CPC分类号： H03M1/144 ,  H03M1/0695 ,  H03M1/468

摘要： Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.

摘要翻译： 提供了用于通过在多个逐次逼近循环中处理每个周期多于一个比特来将模拟信号转换为数字信号的实例。 系统可以包括电容式子DAC电路和比较器。 开关可以在一个或多个第一周期期间隔离电容性的次DAC电路，并且在一个或多个最后一个周期期间合并子DAC电路。 逐次逼近寄存器（SAR）可以产生数字输出信号或DAC数字信号。 在另一示例中，系统可以包括DAC电路。 输入电容器可以被预先充电到模拟输入信号和DAC模拟信号中的至少一个。 可编程增益放大器可以放大误差信号。 多位ADC可将放大的误差信号转换为多位数字信号。 SAR可以使用多位数字信号来产生DAC数字信号或数字输出信号。

公开(公告)号：US20130120176A1

公开(公告)日：2013-05-16

申请号：US13296185

申请日：2011-11-14

申请人： Ark-Chew WONG ,  Jonathan Muller

发明人： Ark-Chew WONG ,  Jonathan Muller

IPC分类号： H03M1/66

CPC分类号： H03M1/808 ,  H03M1/1061 ,  H03M1/687 ,  H03M1/785

摘要： Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal.

摘要翻译： 本文提供了电阻数模转换器（RDAC）电路的示例。 RDAC电路可以提供从n位数字输入信号导出的模拟输出信号。 在一个示例中，RDAC电路可以包括多个电阻电路分支。 每个电阻电路分支可以布置成上拉/下拉网络配置。 例如，RDAC电路可以包括并联设置的多个电阻电路分支。 在一个示例中，多个电阻电路分支中的每一个可以包括第一反相器电路，第二反相器电路和电阻部件。 RDAC电路可以包括用于提供模拟输出信号的输出节点。 此外，提供了用于转换从n位数字输入信号导出的模拟输出信号的方法。

公开(公告)号：US08183885B2

公开(公告)日：2012-05-22

申请号：US12384795

申请日：2009-04-08

申请人： Joseph Aziz ,  Andrew Chen ,  Ark-Chew Wong ,  Derek Tam

发明人： Joseph Aziz ,  Andrew Chen ,  Ark-Chew Wong ,  Derek Tam

IPC分类号： H03K19/094

CPC分类号： H03K19/017581 ,  H04L25/0282

摘要： In one embodiment, a circuit for providing a tail current for a line driver includes an adjustable current source. The adjustable current source includes a number of current source cells coupled together in a parallel configuration, where the current source cells are configured to provide the tail current for the line driver in response to a digital control signal. The circuit can further include a digital core coupled to the adjustable current source, where the digital core provides the digital control signal. The digital control signal provides a number of bits, where each bit controls one of the current source cells. In one embodiment, a current source cell can comprise a number of current source sub-cells. The current source cells can be configured to provide the tail current for the line driver in response to the digital control signal when the line driver is operating in a class AB mode.

摘要翻译： 在一个实施例中，用于为线路驱动器提供尾电流的电路包括可调电流源。 可调电流源包括以并联配置耦合在一起的多个电流源电池，其中电流源单元被配置为响应于数字控制信号为线路驱动器提供尾电流。 该电路还可以包括耦合到可调节电流源的数字核心，其中数字核心提供数字控制信号。 数字控制信号提供多个位，其中每个位控制当前源单元之一。 在一个实施例中，电流源单元可以包括多个电流源子单元。 当线路驱动器在AB类模式下操作时，当前源单元可被配置为响应于数字控制信号为线路驱动器提供尾电流。

公开(公告)号：US20100259340A1

公开(公告)日：2010-10-14

申请号：US12384793

申请日：2009-04-08

申请人： Joseph Aziz ,  Andrew Chen ,  Derek Tam ,  Ark-Chew Wong ,  Agnes Neves Woo ,  Marcel Lugthart

发明人： Joseph Aziz ,  Andrew Chen ,  Derek Tam ,  Ark-Chew Wong ,  Agnes Neves Woo ,  Marcel Lugthart

IPC分类号： H03H7/38

CPC分类号： H04L25/0298

摘要： According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.

摘要翻译： 根据一个示例性实施例，有源终端电路包括至少一个有源终端分支，其中所述至少一个有源终端分支包括用于提供有源终端输出的至少一个晶体管。 所述至少一个有源终端分支还包括驱动所述至少一个晶体管的放大器，其中所述放大器具有经由反馈网络耦合到所述有源终端输出的非反相输入。 放大器控制流过至少一个晶体管的电流，以便提供有源终端输出。 可以在至少一个晶体管的漏极处提供有源终端输出，其中至少一个晶体管的源极通过退化晶体管和尾部电流吸收器耦合到地。

公开(公告)号：US07642946B2

公开(公告)日：2010-01-05

申请号：US12098842

申请日：2008-04-07

申请人： Ark-Chew Wong ,  Marcel L. Lugthart ,  Andrew R. Chen

发明人： Ark-Chew Wong ,  Marcel L. Lugthart ,  Andrew R. Chen

IPC分类号： H03M1/34

CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/46 ,  H03M1/742 ,  H03M1/765 ,  H03M1/785

摘要： A system and method are provided allowing for successive approximation analog to digital conversion. A first differential voltage is sampled and held during a first cycle. The first differential voltage is converted to a differential current. A second differential voltage is generated based on the differential current flowing through parallel-coupled respective first and second variable resistances. First and second portions of the second differential voltage are compared to produce a comparison result therefrom. Successive approximation is used to generate a signal based on the comparison result, the signal being an output signal and being used to control resistances of respective ones of the first and second variable resistances during subsequent cycles.

摘要翻译： 提供了允许逐次逼近模数转换的系统和方法。 在第一周期期间对第一差分电压进行采样和保持。 第一差分电压被转换为差分电流。 基于流过并联耦合的相应的第一和第二可变电阻的差分电流产生第二差分电压。 比较第二差分电压的第一和第二部分以产生比较结果。 使用逐次近似来生成基于比较结果的信号，该信号是输出信号，并用于在随后的周期期间控制第一和第二可变电阻中的相应电阻的电阻。

公开(公告)号：US08847811B2

公开(公告)日：2014-09-30

申请号：US13369093

申请日：2012-02-08

申请人： Ark-Chew Wong ,  Olivier Jacques Nys ,  Jonathan Muller

发明人： Ark-Chew Wong ,  Olivier Jacques Nys ,  Jonathan Muller

IPC分类号： H03M1/34

CPC分类号： H03M1/125 ,  H03M1/42

摘要： Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage.

摘要翻译： 提供了使用串行纹波模数转换（ADC）将模拟信号转换为数字输出信号的示例。 ADC电路可以包括串联耦合的转换级。 每个转换级可以产生数字输出信号的位。 数据锁存器可以接收来自转换级的数字输出信号的位，并且基于位提供数字输出信号。 转换级可以包括比较器电路和多路复用器电路。 比较器电路可以将采样的输入信号与参考信号进行比较，并且基于比较的结果产生数字输出信号的相关位。 多路复用器电路可以向下一个转换级的比较器电路提供相关联的参考信号，其中下一个转换级在转换级之后。

公开(公告)号：US08593325B2

公开(公告)日：2013-11-26

申请号：US13287978

申请日：2011-11-02

申请人： Ark-Chew Wong ,  Olivier Jacques Nys

发明人： Ark-Chew Wong ,  Olivier Jacques Nys

IPC分类号： H03M1/34

CPC分类号： H03M1/46 ,  H03M1/747

摘要： Examples of systems and methods are provided for converting an analog input signal to a digital output signal. A system may include a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current. A comparator circuit may be configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal. A successive approximation register circuit may be configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal. The DAC-code signal may be used by the CM DAC circuit to control the DAC current.

摘要翻译： 提供了用于将模拟输入信号转换为数字输出信号的系统和方法的示例。 系统可以包括提供DAC电流的电流模式（CM）数模转换器（DAC）电路。 比较器电路可以被配置为响应于基于DAC电流和模拟输入信号确定的误差信号而产生比较器信号。 逐次逼近寄存器电路可以被配置为响应于比较器信号而产生DAC代码信号或数字输出信号中的至少一个。 DAC代码信号可被CM DAC电路用于控制DAC电流。

公开(公告)号：US20110204967A1

公开(公告)日：2011-08-25

申请号：US12660430

申请日：2010-02-25

申请人： Ark-Chew Wong ,  Joseph Aziz ,  Derek Tam ,  Kevin Chan

发明人： Ark-Chew Wong ,  Joseph Aziz ,  Derek Tam ,  Kevin Chan

IPC分类号： H04B3/00

CPC分类号： H04B3/30 ,  H04L25/0272

摘要： Disclosed is a false-link protection circuit comprising at least one native switch coupled between a communication terminal of a first differential switch and a communication terminal of a second differential switch. The at least one native switch is configured to provide an attenuation path for a pulse link signal received by either communication terminal when the first and second differential switches are in a powered down state. According to one embodiment, a method to attenuate a pulse link signal comprises activating a native switch of a false-link protection circuit by powering down first and second differential switches, receiving a pulse link signal at a communication terminal of one of the first and second differential switches, and attenuating the pulse link signal by diverting it through the false-link protection circuit when the first and second differential switches are in a powered down state.

摘要翻译： 公开了一种假连接保护电路，其包括耦合在第一差分开关的通信终端和第二差分开关的通信终端之间的至少一个本地开关。 至少一个本地开关被配置为当第一和第二差分开关处于断电状态时，为通信终端接收的脉冲链路信号提供衰减路径。 根据一个实施例，一种衰减脉冲链路信号的方法包括通过断电第一和第二差分开关来激活假链路保护电路的本地交换机，在第一和第二差分开关之一的通信终端处接收脉冲链路信号 差分开关，并且当第一和第二差分开关处于掉电状态时，通过将其通过假链路保护电路分流来衰减脉冲链路信号。

公开(公告)号：US06667558B2

公开(公告)日：2003-12-23

申请号：US10413189

申请日：2003-04-14

申请人： Ark-Chew Wong ,  Clark T.-C. Nguyen

发明人： Ark-Chew Wong ,  Clark T.-C. Nguyen

IPC分类号： H01L2348

CPC分类号： B81B7/007 ,  B81B2203/0361 ,  B81C1/00253 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/038 ,  B81C2203/051 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/3011

摘要： A module bonded together at a microplatform and an improved method for making the module are provided. The method includes providing a micromechanical device including a first substrate, the microplatform, a first plurality of bonding sites on the microplatform, a micromechanical structure fabricated and supported on the microplatform and a support structure to suspend the microplatform above the first substrate. The method further includes providing a transistor circuit wafer including a second plurality of bonding sites thereon and integrated BiCMOS transistor circuits. The first and second plurality of bonding sites are aligned and compression bonded so that the microplatform is both electrically and mechanically coupled to the second substrate to form the module. The platform carrier wafer can be torn off, leaving bonded platforms behind on the substrate wafer. This allows small form factor merging of the two different technologies.